net: stmmac: use interrupt mode INTM=1 for multi-MSI
authorWong, Vee Khee <vee.khee.wong@intel.com>
Thu, 25 Mar 2021 17:39:16 +0000 (01:39 +0800)
committerDavid S. Miller <davem@davemloft.net>
Fri, 26 Mar 2021 00:37:30 +0000 (17:37 -0700)
For interrupt mode INTM=0, TX/RX transfer complete will trigger signal
not only on sbd_perch_[tx|rx]_intr_o (Transmit/Receive Per Channel) but
also on the sbd_intr_o (Common).

As for multi-MSI implementation, setting interrupt mode INTM=1 is more
efficient as each TX intr and RX intr (TI/RI) will be handled by TX/RX ISR
without the need of calling the common MAC ISR.

Updated the TX/RX NORMAL interrupts status checking process as the
NIS status bit is not asserted for any RI/TI events for INTM=1.

Signed-off-by: Wong, Vee Khee <vee.khee.wong@intel.com>
Co-developed-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: Voon Weifeng <weifeng.voon@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.h
drivers/net/ethernet/stmicro/stmmac/dwmac4_lib.c
drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
include/linux/stmmac.h

index 8954b85..cb17f6c 100644 (file)
@@ -161,6 +161,13 @@ static void dwmac4_dma_init(void __iomem *ioaddr,
                value |= DMA_SYS_BUS_EAME;
 
        writel(value, ioaddr + DMA_SYS_BUS_MODE);
+
+       if (dma_cfg->multi_msi_en) {
+               value = readl(ioaddr + DMA_BUS_MODE);
+               value &= ~DMA_BUS_MODE_INTM_MASK;
+               value |= (DMA_BUS_MODE_INTM_MODE1 << DMA_BUS_MODE_INTM_SHIFT);
+               writel(value, ioaddr + DMA_BUS_MODE);
+       }
 }
 
 static void _dwmac4_dump_dma_regs(void __iomem *ioaddr, u32 channel,
index 5c0c538..05481eb 100644 (file)
@@ -25,6 +25,9 @@
 #define DMA_TBS_CTRL                   0x00001050
 
 /* DMA Bus Mode bitmap */
+#define DMA_BUS_MODE_INTM_MASK         GENMASK(17, 16)
+#define DMA_BUS_MODE_INTM_SHIFT                16
+#define DMA_BUS_MODE_INTM_MODE1                0x1
 #define DMA_BUS_MODE_SFT_RESET         BIT(0)
 
 /* DMA SYS Bus Mode bitmap */
index 3fa602d..e632702 100644 (file)
@@ -166,20 +166,19 @@ int dwmac4_dma_interrupt(void __iomem *ioaddr,
                }
        }
        /* TX/RX NORMAL interrupts */
-       if (likely(intr_status & DMA_CHAN_STATUS_NIS)) {
+       if (likely(intr_status & DMA_CHAN_STATUS_NIS))
                x->normal_irq_n++;
-               if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
-                       x->rx_normal_irq_n++;
-                       ret |= handle_rx;
-               }
-               if (likely(intr_status & (DMA_CHAN_STATUS_TI |
-                                         DMA_CHAN_STATUS_TBU))) {
-                       x->tx_normal_irq_n++;
-                       ret |= handle_tx;
-               }
-               if (unlikely(intr_status & DMA_CHAN_STATUS_ERI))
-                       x->rx_early_irq++;
+       if (likely(intr_status & DMA_CHAN_STATUS_RI)) {
+               x->rx_normal_irq_n++;
+               ret |= handle_rx;
+       }
+       if (likely(intr_status & (DMA_CHAN_STATUS_TI |
+               DMA_CHAN_STATUS_TBU))) {
+               x->tx_normal_irq_n++;
+               ret |= handle_tx;
        }
+       if (unlikely(intr_status & DMA_CHAN_STATUS_ERI))
+               x->rx_early_irq++;
 
        writel(intr_status & intr_en, ioaddr + DMA_CHAN_STATUS(chan));
        return ret;
index 459477d..f4fa540 100644 (file)
@@ -5620,6 +5620,7 @@ int stmmac_dvr_probe(struct device *device,
        priv->plat = plat_dat;
        priv->ioaddr = res->addr;
        priv->dev->base_addr = (unsigned long)res->addr;
+       priv->plat->dma_cfg->multi_msi_en = priv->plat->multi_msi_en;
 
        priv->dev->irq = res->irq;
        priv->wol_irq = res->wol_irq;
index afc12b9..e338ef7 100644 (file)
@@ -96,6 +96,7 @@ struct stmmac_dma_cfg {
        int mixed_burst;
        bool aal;
        bool eame;
+       bool multi_msi_en;
 };
 
 #define AXI_BLEN       7