spi: sh-msiof: SITMDR1/SIRMDR1 bitfield conversion

Convert MSIOF Transmit and Receive Mode Register 1 field accesses to use
the FIELD_PREP() bitfield access macro.

This gets rid of explicit shifts.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/9685c54e752b8ef4256c9b281e9d8292e71d222e.1747401908.git.geert+renesas@glider.be
Signed-off-by: Mark Brown <broonie@kernel.org>

diff --git a/drivers/spi/spi-sh-msiof.c b/drivers/spi/spi-sh-msiof.c
index 7c15de0..fb83b04 100644 (file)
--- a/drivers/spi/spi-sh-msiof.c
+++ b/drivers/spi/spi-sh-msiof.c
@@ -7,6 +7,7 @@
  * Copyright (C) 2014-2017 Glider bvba
  */
 
+#include <linux/bitfield.h>
 #include <linux/bitmap.h>
 #include <linux/clk.h>
 #include <linux/completion.h>
@@ -84,20 +85,19 @@ struct sh_msiof_spi_priv {
 
 /* SITMDR1 and SIRMDR1 */
 #define SIMDR1_TRMD            BIT(31)         /* Transfer Mode (1 = Master mode) */
-#define SIMDR1_SYNCMD_MASK     GENMASK(29, 28) /* SYNC Mode */
-#define SIMDR1_SYNCMD_SPI      (2 << 28)       /*   Level mode/SPI */
-#define SIMDR1_SYNCMD_LR       (3 << 28)       /*   L/R mode */
-#define SIMDR1_SYNCAC_SHIFT    25              /* Sync Polarity (1 = Active-low) */
-#define SIMDR1_BITLSB_SHIFT    24              /* MSB/LSB First (1 = LSB first) */
-#define SIMDR1_DTDL_SHIFT      20              /* Data Pin Bit Delay for MSIOF_SYNC */
-#define SIMDR1_SYNCDL_SHIFT    16              /* Frame Sync Signal Timing Delay */
-#define SIMDR1_FLD_MASK                GENMASK(3, 2)   /* Frame Sync Signal Interval (0-3) */
-#define SIMDR1_FLD_SHIFT       2
+#define SIMDR1_SYNCMD          GENMASK(29, 28) /* SYNC Mode */
+#define SIMDR1_SYNCMD_SPI      2U              /*   Level mode/SPI */
+#define SIMDR1_SYNCMD_LR       3U              /*   L/R mode */
+#define SIMDR1_SYNCAC          BIT(25)         /* Sync Polarity (1 = Active-low) */
+#define SIMDR1_BITLSB          BIT(24)         /* MSB/LSB First (1 = LSB first) */
+#define SIMDR1_DTDL            GENMASK(22, 20) /* Data Pin Bit Delay for MSIOF_SYNC */
+#define SIMDR1_SYNCDL          GENMASK(18, 16) /* Frame Sync Signal Timing Delay */
+#define SIMDR1_FLD             GENMASK(3, 2)   /* Frame Sync Signal Interval (0-3) */
 #define SIMDR1_XXSTP           BIT(0)          /* Transmission/Reception Stop on FIFO */
 /* SITMDR1 */
 #define SITMDR1_PCON           BIT(30)         /* Transfer Signal Connection */
-#define SITMDR1_SYNCCH_MASK    GENMASK(27, 26) /* Sync Signal Channel Select */
-#define SITMDR1_SYNCCH_SHIFT   26              /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
+#define SITMDR1_SYNCCH         GENMASK(27, 26) /* Sync Signal Channel Select */
+                                               /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */
 
 /* SITMDR2 and SIRMDR2 */
 #define SIMDR2_BITLEN1(i)      (((i) - 1) << 24) /* Data Size (8-32 bits) */
@@ -341,8 +341,9 @@ static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p)
                return 0;
        }
 
-       val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT;
-       val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT;
+       val = FIELD_PREP(SIMDR1_DTDL, sh_msiof_get_delay_bit(p->info->dtdl)) |
+             FIELD_PREP(SIMDR1_SYNCDL,
+                        sh_msiof_get_delay_bit(p->info->syncdl));
 
        return val;
 }
@@ -361,16 +362,18 @@ static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss,
         *    1    0         11     11    0    0
         *    1    1         11     11    1    1
         */
-       tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP;
-       tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT;
-       tmp |= lsb_first << SIMDR1_BITLSB_SHIFT;
+       tmp = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI) |
+             FIELD_PREP(SIMDR1_FLD, 1) | SIMDR1_XXSTP |
+             FIELD_PREP(SIMDR1_SYNCAC, !cs_high) |
+             FIELD_PREP(SIMDR1_BITLSB, lsb_first);
        tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p);
        if (spi_controller_is_target(p->ctlr)) {
                sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON);
        } else {
                sh_msiof_write(p, SITMDR1,
                               tmp | SIMDR1_TRMD | SITMDR1_PCON |
-                              (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT);
+                              FIELD_PREP(SITMDR1_SYNCCH,
+                                         ss < MAX_SS ? ss : 0));
        }
        if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) {
                /* These bits are reserved if RX needs TX */
@@ -579,12 +582,12 @@ static int sh_msiof_spi_setup(struct spi_device *spi)
                return 0;
 
        /* Configure native chip select mode/polarity early */
-       clr = SIMDR1_SYNCMD_MASK;
-       set = SIMDR1_SYNCMD_SPI;
+       clr = SIMDR1_SYNCMD;
+       set = FIELD_PREP(SIMDR1_SYNCMD, SIMDR1_SYNCMD_SPI);
        if (spi->mode & SPI_CS_HIGH)
-               clr |= BIT(SIMDR1_SYNCAC_SHIFT);
+               clr |= SIMDR1_SYNCAC;
        else
-               set |= BIT(SIMDR1_SYNCAC_SHIFT);
+               set |= SIMDR1_SYNCAC;
        pm_runtime_get_sync(&p->pdev->dev);
        tmp = sh_msiof_read(p, SITMDR1) & ~clr;
        sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON);