Merge branch 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...

Pull x86 cpu updates from Ingo Molnar:
 "Two changes: a suspend/resume quirk and a new CPUID bit definition"

* 'x86-cpu-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/cpufeature: Add feature bit for Intel's Silicon Debug CPUID bit
  x86/cpu: Restore MSR_IA32_ENERGY_PERF_BIAS after resume

diff --combined arch/x86/include/asm/cpufeature.h
index a39e570,4b11974..477fc28
--- 1/arch/x86/include/asm/cpufeature.h
--- 2/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@@ -119,6 -119,7 +119,7 @@@
  #define X86_FEATURE_TM2               ( 4*32+ 8) /* Thermal Monitor 2 */
  #define X86_FEATURE_SSSE3     ( 4*32+ 9) /* Supplemental SSE-3 */
  #define X86_FEATURE_CID               ( 4*32+10) /* Context ID */
+ #define X86_FEATURE_SDBG      ( 4*32+11) /* Silicon Debug */
  #define X86_FEATURE_FMA               ( 4*32+12) /* Fused multiply-add */
  #define X86_FEATURE_CX16      ( 4*32+13) /* CMPXCHG16B */
  #define X86_FEATURE_XTPR      ( 4*32+14) /* Send Task Priority Messages */
@@@ -176,7 -177,6 +177,7 @@@
  #define X86_FEATURE_PERFCTR_NB  ( 6*32+24) /* NB performance counter extensions */
  #define X86_FEATURE_BPEXT     (6*32+26) /* data breakpoint extension */
  #define X86_FEATURE_PERFCTR_L2        ( 6*32+28) /* L2 performance counter extensions */
 +#define X86_FEATURE_MWAITX    ( 6*32+29) /* MWAIT extension (MONITORX/MWAITX) */
  
  /*
   * Auxiliary flags: Linux defined - For features scattered in various

diff --combined arch/x86/kernel/cpu/common.c
index b128808,fa95bb8..07ce52c
--- 1/arch/x86/kernel/cpu/common.c
--- 2/arch/x86/kernel/cpu/common.c
+++ b/arch/x86/kernel/cpu/common.c
@@@ -13,6 -13,7 +13,7 @@@
  #include <linux/kgdb.h>
  #include <linux/smp.h>
  #include <linux/io.h>
+ #include <linux/syscore_ops.h>
  
  #include <asm/stackprotector.h>
  #include <asm/perf_event.h>
@@@ -1185,10 -1186,10 +1186,10 @@@ void syscall_init(void
         * set CS/DS but only a 32bit target. LSTAR sets the 64bit rip.
         */
        wrmsrl(MSR_STAR,  ((u64)__USER32_CS)<<48  | ((u64)__KERNEL_CS)<<32);
 -      wrmsrl(MSR_LSTAR, entry_SYSCALL_64);
 +      wrmsrl(MSR_LSTAR, (unsigned long)entry_SYSCALL_64);
  
  #ifdef CONFIG_IA32_EMULATION
 -      wrmsrl(MSR_CSTAR, entry_SYSCALL_compat);
 +      wrmsrl(MSR_CSTAR, (unsigned long)entry_SYSCALL_compat);
        /*
         * This only works on Intel CPUs.
         * On AMD CPUs these MSRs are 32-bit, CPU truncates MSR_IA32_SYSENTER_EIP.
@@@ -1199,7 -1200,7 +1200,7 @@@
        wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
        wrmsrl_safe(MSR_IA32_SYSENTER_EIP, (u64)entry_SYSENTER_compat);
  #else
 -      wrmsrl(MSR_CSTAR, ignore_sysret);
 +      wrmsrl(MSR_CSTAR, (unsigned long)ignore_sysret);
        wrmsrl_safe(MSR_IA32_SYSENTER_CS, (u64)GDT_ENTRY_INVALID_SEG);
        wrmsrl_safe(MSR_IA32_SYSENTER_ESP, 0ULL);
        wrmsrl_safe(MSR_IA32_SYSENTER_EIP, 0ULL);
@@@ -1410,7 -1411,7 +1411,7 @@@ void cpu_init(void
        load_sp0(t, &current->thread);
        set_tss_desc(cpu, t);
        load_TR_desc();
 -      load_LDT(&init_mm.context);
 +      load_mm_ldt(&init_mm);
  
        clear_all_debug_regs();
        dbg_restore_debug_regs();
@@@ -1459,7 -1460,7 +1460,7 @@@ void cpu_init(void
        load_sp0(t, thread);
        set_tss_desc(cpu, t);
        load_TR_desc();
 -      load_LDT(&init_mm.context);
 +      load_mm_ldt(&init_mm);
  
        t->x86_tss.io_bitmap_base = offsetof(struct tss_struct, io_bitmap);
  
@@@ -1488,3 -1489,20 +1489,20 @@@ inline bool __static_cpu_has_safe(u16 b
        return boot_cpu_has(bit);
  }
  EXPORT_SYMBOL_GPL(__static_cpu_has_safe);
+ 
+ static void bsp_resume(void)
+ {
+       if (this_cpu->c_bsp_resume)
+               this_cpu->c_bsp_resume(&boot_cpu_data);
+ }
+ 
+ static struct syscore_ops cpu_syscore_ops = {
+       .resume         = bsp_resume,
+ };
+ 
+ static int __init init_cpu_syscore(void)
+ {
+       register_syscore_ops(&cpu_syscore_ops);
+       return 0;
+ }
+ core_initcall(init_cpu_syscore);