drm/amdgpu: update the handle ptr in check_soft_reset
authorSunil Khatri <sunil.khatri@amd.com>
Mon, 30 Sep 2024 09:02:13 +0000 (14:32 +0530)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 1 Oct 2024 21:43:45 +0000 (17:43 -0400)
Update the *handle to amdgpu_ip_block ptr for all
functions pointers of check_soft_reset.

Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
15 files changed:
drivers/gpu/drm/amd/amdgpu/amdgpu_device.c
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v6_0.c
drivers/gpu/drm/amd/amdgpu/sdma_v7_0.c
drivers/gpu/drm/amd/amdgpu/tonga_ih.c
drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
drivers/gpu/drm/amd/include/amd_shared.h

index e79370d..d66f764 100644 (file)
@@ -4949,7 +4949,8 @@ static bool amdgpu_device_ip_check_soft_reset(struct amdgpu_device *adev)
                        continue;
                if (adev->ip_blocks[i].version->funcs->check_soft_reset)
                        adev->ip_blocks[i].status.hang =
-                               adev->ip_blocks[i].version->funcs->check_soft_reset(adev);
+                               adev->ip_blocks[i].version->funcs->check_soft_reset(
+                                       &adev->ip_blocks[i]);
                if (adev->ip_blocks[i].status.hang) {
                        dev_info(adev->dev, "IP block:%s is hung!\n", adev->ip_blocks[i].version->funcs->name);
                        asic_hang = true;
index cac0850..4eb3313 100644 (file)
@@ -2953,9 +2953,9 @@ static int dce_v10_0_wait_for_idle(void *handle)
        return 0;
 }
 
-static bool dce_v10_0_check_soft_reset(void *handle)
+static bool dce_v10_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
 
        return dce_v10_0_is_display_hung(adev);
 }
index a190c0b..df08f29 100644 (file)
@@ -4907,10 +4907,10 @@ static int gfx_v11_0_soft_reset(void *handle)
        return gfx_v11_0_cp_resume(adev);
 }
 
-static bool gfx_v11_0_check_soft_reset(void *handle)
+static bool gfx_v11_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        int i, r;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        struct amdgpu_ring *ring;
        long tmo = msecs_to_jiffies(1000);
 
index a6a3871..d14a341 100644 (file)
@@ -4921,9 +4921,9 @@ static int gfx_v8_0_resume(void *handle)
        return gfx_v8_0_hw_init(handle);
 }
 
-static bool gfx_v8_0_check_soft_reset(void *handle)
+static bool gfx_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 grbm_soft_reset = 0, srbm_soft_reset = 0;
        u32 tmp;
 
index 2354756..0d300f5 100644 (file)
@@ -1289,10 +1289,10 @@ static int gmc_v8_0_wait_for_idle(void *handle)
 
 }
 
-static bool gmc_v8_0_check_soft_reset(void *handle)
+static bool gmc_v8_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        u32 srbm_soft_reset = 0;
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
        if (tmp & SRBM_STATUS__VMC_BUSY_MASK)
index 1b73bbb..7e2a523 100644 (file)
@@ -1231,9 +1231,9 @@ static int sdma_v3_0_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static bool sdma_v3_0_check_soft_reset(void *handle)
+static bool sdma_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS2);
 
index d4eb1cb..edf8f23 100644 (file)
@@ -791,9 +791,9 @@ static int sdma_v6_0_soft_reset(void *handle)
        return sdma_v6_0_start(adev);
 }
 
-static bool sdma_v6_0_check_soft_reset(void *handle)
+static bool sdma_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        struct amdgpu_ring *ring;
        int i, r;
        long tmo = msecs_to_jiffies(1000);
index 3c017db..691870e 100644 (file)
@@ -783,9 +783,9 @@ static int sdma_v7_0_soft_reset(void *handle)
        return sdma_v7_0_start(adev);
 }
 
-static bool sdma_v7_0_check_soft_reset(void *handle)
+static bool sdma_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        struct amdgpu_ring *ring;
        int i, r;
        long tmo = msecs_to_jiffies(1000);
index bfcf672..573a2e1 100644 (file)
@@ -386,9 +386,9 @@ static int tonga_ih_wait_for_idle(void *handle)
        return -ETIMEDOUT;
 }
 
-static bool tonga_ih_check_soft_reset(void *handle)
+static bool tonga_ih_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
index 642b8db..7364cec 100644 (file)
@@ -1164,9 +1164,9 @@ static int uvd_v6_0_wait_for_idle(void *handle)
 }
 
 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
-static bool uvd_v6_0_check_soft_reset(void *handle)
+static bool uvd_v6_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
index aef7ca1..52d613b 100644 (file)
@@ -1484,9 +1484,9 @@ static int uvd_v7_0_wait_for_idle(void *handle)
 }
 
 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
-static bool uvd_v7_0_check_soft_reset(void *handle)
+static bool uvd_v7_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
        u32 tmp = RREG32(mmSRBM_STATUS);
 
index 3edd339..6a8f555 100644 (file)
@@ -627,9 +627,9 @@ static int vce_v3_0_wait_for_idle(void *handle)
 #define  AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
                                      VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
 
-static bool vce_v3_0_check_soft_reset(void *handle)
+static bool vce_v3_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
 
        /* According to VCE team , we should use VCE_STATUS instead
index 8ba0e3a..c89ae2d 100644 (file)
@@ -721,9 +721,9 @@ static int vce_v4_0_wait_for_idle(void *handle)
 #define  AMDGPU_VCE_STATUS_BUSY_MASK (VCE_STATUS_VCPU_REPORT_AUTO_BUSY_MASK | \
                                      VCE_STATUS_VCPU_REPORT_RB0_BUSY_MASK)
 
-static bool vce_v4_0_check_soft_reset(void *handle)
+static bool vce_v4_0_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
-       struct amdgpu_device *adev = (struct amdgpu_device *)handle;
+       struct amdgpu_device *adev = ip_block->adev;
        u32 srbm_soft_reset = 0;
 
        /* According to VCE team , we should use VCE_STATUS instead
index e222062..51d692f 100644 (file)
@@ -326,7 +326,7 @@ static int dm_wait_for_idle(void *handle)
        return 0;
 }
 
-static bool dm_check_soft_reset(void *handle)
+static bool dm_check_soft_reset(struct amdgpu_ip_block *ip_block)
 {
        return false;
 }
index 1939c0d..1130dac 100644 (file)
@@ -392,7 +392,7 @@ struct amd_ip_funcs {
        int (*resume)(void *handle);
        bool (*is_idle)(void *handle);
        int (*wait_for_idle)(void *handle);
-       bool (*check_soft_reset)(void *handle);
+       bool (*check_soft_reset)(struct amdgpu_ip_block *ip_block);
        int (*pre_soft_reset)(void *handle);
        int (*soft_reset)(void *handle);
        int (*post_soft_reset)(void *handle);