drm/xe: Correct lineage for Wa_22014953428 and only check with valid GT
authorMatt Roper <matthew.d.roper@intel.com>
Mon, 13 Oct 2025 20:10:01 +0000 (13:10 -0700)
committerMatt Roper <matthew.d.roper@intel.com>
Tue, 14 Oct 2025 14:45:17 +0000 (07:45 -0700)
Wa_22014953428 was incorrectly labelled with a release-specific ID
number rather than the cross-platform lineage number; fix that.
Also check that the GT is not NULL before trying to lookup the
workaround in it.  Since this workaround only applies to DG2 discrete
GPUs (where the primary GT cannot be disabled), no coverage is lost.

Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Link: https://lore.kernel.org/r/20251013200944.2499947-43-matthew.d.roper@intel.com
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
drivers/gpu/drm/xe/xe_vm.c
drivers/gpu/drm/xe/xe_wa_oob.rules

index 179758c..08bc55b 100644 (file)
@@ -1910,6 +1910,7 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
        struct xe_device *xe = to_xe_device(dev);
        struct xe_file *xef = to_xe_file(file);
        struct drm_xe_vm_create *args = data;
+       struct xe_gt *wa_gt = xe_root_mmio_gt(xe);
        struct xe_vm *vm;
        u32 id;
        int err;
@@ -1918,7 +1919,7 @@ int xe_vm_create_ioctl(struct drm_device *dev, void *data,
        if (XE_IOCTL_DBG(xe, args->extensions))
                return -EINVAL;
 
-       if (XE_GT_WA(xe_root_mmio_gt(xe), 14016763929))
+       if (wa_gt && XE_GT_WA(wa_gt, 22014953428))
                args->flags |= DRM_XE_VM_CREATE_FLAG_SCRATCH_PAGE;
 
        if (XE_IOCTL_DBG(xe, args->flags & DRM_XE_VM_CREATE_FLAG_FAULT_MODE &&
index 113a62f..4bb94e5 100644 (file)
@@ -11,7 +11,7 @@
 18020744125    PLATFORM(PVC)
 1509372804     PLATFORM(PVC), GRAPHICS_STEP(A0, C0)
 1409600907     GRAPHICS_VERSION_RANGE(1200, 1250)
-14016763929    SUBPLATFORM(DG2, G10)
+22014953428    SUBPLATFORM(DG2, G10)
                SUBPLATFORM(DG2, G12)
 16017236439    PLATFORM(PVC)
 14019821291    MEDIA_VERSION_RANGE(1300, 2000)