drm/amd/display: Add warmup escape call support

Add warmup escape support, for diags, in a way that is possible to
choose a new or an existing sequence. For achieving this goal, this
commit adds separated MCIF buffer as VCN request.

Signed-off-by: Charlene Liu <charlene.liu@amd.com>
Reviewed-by: Chris Park <Chris.Park@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
index b43a4b1..6ddbb00 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_stream.c
@@ -406,25 +406,30 @@ bool dc_stream_add_writeback(struct dc *dc,
                stream->writeback_info[stream->num_wb_info++] = *wb_info;
        }
 
-       if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
-               dm_error("DC: update_bandwidth failed!\n");
-               return false;
-       }
-
-       /* enable writeback */
        if (dc->hwss.enable_writeback) {
                struct dc_stream_status *stream_status = dc_stream_get_status(stream);
                struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+               dwb->otg_inst = stream_status->primary_otg_inst;
+       }
+       if (IS_DIAG_DC(dc->ctx->dce_environment)) {
+               if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
+                       dm_error("DC: update_bandwidth failed!\n");
+                       return false;
+               }
 
-               if (dwb->funcs->is_enabled(dwb)) {
-                       /* writeback pipe already enabled, only need to update */
-                       dc->hwss.update_writeback(dc, stream_status, wb_info, dc->current_state);
-               } else {
-                       /* Enable writeback pipe from scratch*/
-                       dc->hwss.enable_writeback(dc, stream_status, wb_info, dc->current_state);
+               /* enable writeback */
+               if (dc->hwss.enable_writeback) {
+                       struct dwbc *dwb = dc->res_pool->dwbc[wb_info->dwb_pipe_inst];
+
+                       if (dwb->funcs->is_enabled(dwb)) {
+                               /* writeback pipe already enabled, only need to update */
+                               dc->hwss.update_writeback(dc, wb_info, dc->current_state);
+                       } else {
+                               /* Enable writeback pipe from scratch*/
+                               dc->hwss.enable_writeback(dc, wb_info, dc->current_state);
+                       }
                }
        }
-
        return true;
 }
 
@@ -463,19 +468,29 @@ bool dc_stream_remove_writeback(struct dc *dc,
        }
        stream->num_wb_info = j;
 
-       /* recalculate and apply DML parameters */
-       if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
-               dm_error("DC: update_bandwidth failed!\n");
-               return false;
-       }
-
-       /* disable writeback */
-       if (dc->hwss.disable_writeback)
-               dc->hwss.disable_writeback(dc, dwb_pipe_inst);
+       if (IS_DIAG_DC(dc->ctx->dce_environment)) {
+               /* recalculate and apply DML parameters */
+               if (!dc->hwss.update_bandwidth(dc, dc->current_state)) {
+                       dm_error("DC: update_bandwidth failed!\n");
+                       return false;
+               }
 
+               /* disable writeback */
+               if (dc->hwss.disable_writeback)
+                       dc->hwss.disable_writeback(dc, dwb_pipe_inst);
+       }
        return true;
 }
 
+bool dc_stream_warmup_writeback(struct dc *dc,
+               int num_dwb,
+               struct dc_writeback_info *wb_info)
+{
+       if (dc->hwss.mmhubbub_warmup)
+               return dc->hwss.mmhubbub_warmup(dc, num_dwb, wb_info);
+       else
+               return false;
+}
 uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
 {
        uint8_t i;

diff --git a/drivers/gpu/drm/amd/display/dc/dc_stream.h b/drivers/gpu/drm/amd/display/dc/dc_stream.h
index 3ea5432..37c10db 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_stream.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_stream.h
@@ -344,10 +344,17 @@ bool dc_add_all_planes_for_stream(
 bool dc_stream_add_writeback(struct dc *dc,
                struct dc_stream_state *stream,
                struct dc_writeback_info *wb_info);
+
 bool dc_stream_remove_writeback(struct dc *dc,
                struct dc_stream_state *stream,
                uint32_t dwb_pipe_inst);
+
+bool dc_stream_warmup_writeback(struct dc *dc,
+               int num_dwb,
+               struct dc_writeback_info *wb_info);
+
 bool dc_stream_dmdata_status_done(struct dc *dc, struct dc_stream_state *stream);
+
 bool dc_stream_set_dynamic_metadata(struct dc *dc,
                struct dc_stream_state *stream,
                struct dc_dmdata_attributes *dmdata_attr);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
index e1e2740..fb66754 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.c
@@ -1740,7 +1740,6 @@ bool dcn20_update_bandwidth(
 
 void dcn20_enable_writeback(
                struct dc *dc,
-               const struct dc_stream_status *stream_status,
                struct dc_writeback_info *wb_info,
                struct dc_state *context)
 {
@@ -1754,8 +1753,7 @@ void dcn20_enable_writeback(
        mcif_wb = dc->res_pool->mcif_wb[wb_info->dwb_pipe_inst];
 
        /* set the OPTC source mux */
-       ASSERT(stream_status->primary_otg_inst < MAX_PIPES);
-       optc = dc->res_pool->timing_generators[stream_status->primary_otg_inst];
+       optc = dc->res_pool->timing_generators[dwb->otg_inst];
        optc->funcs->set_dwb_source(optc, wb_info->dwb_pipe_inst);
        /* set MCIF_WB buffer and arbitration configuration */
        mcif_wb->funcs->config_mcif_buf(mcif_wb, &wb_info->mcif_buf_params, wb_info->dwb_params.dest_height);

diff --git a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
index eecd7a2..02c9be5 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
+++ b/drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hwseq.h
@@ -104,7 +104,6 @@ void dcn20_program_triple_buffer(
        bool enable_triple_buffer);
 void dcn20_enable_writeback(
                struct dc *dc,
-               const struct dc_stream_status *stream_status,
                struct dc_writeback_info *wb_info,
                struct dc_state *context);
 void dcn20_disable_writeback(

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
index 735f419..459f95f 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h
@@ -113,7 +113,8 @@ struct dwbc {
        int wb_src_plane_inst;/*hubp, mpcc, inst*/
        bool update_privacymask;
        uint32_t mask_id;
-
+        int otg_inst;
+        bool mvc_cfg;
 };
 
 struct dwbc_funcs {

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
index e9c6021..df32046 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw_sequencer.h
@@ -149,16 +149,18 @@ struct hw_sequencer_funcs {
 
        /* Writeback Related */
        void (*update_writeback)(struct dc *dc,
-                       const struct dc_stream_status *stream_status,
                        struct dc_writeback_info *wb_info,
                        struct dc_state *context);
        void (*enable_writeback)(struct dc *dc,
-                       const struct dc_stream_status *stream_status,
                        struct dc_writeback_info *wb_info,
                        struct dc_state *context);
        void (*disable_writeback)(struct dc *dc,
                        unsigned int dwb_pipe_inst);
 
+       bool (*mmhubbub_warmup)(struct dc *dc,
+                       unsigned int num_dwb,
+                       struct dc_writeback_info *wb_info);
+
        /* Clock Related */
        enum dc_status (*set_clock)(struct dc *dc,
                        enum dc_clock_type clock_type,

diff --git a/drivers/gpu/drm/amd/display/include/dal_asic_id.h b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
index 72b659c..11d7daf 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/dal_asic_id.h
+++ b/drivers/gpu/drm/amd/display/include/dal_asic_id.h
@@ -138,10 +138,14 @@
 #define RAVEN2_15D8_REV_E4 0xE4
 #define RAVEN1_F0 0xF0
 #define RAVEN_UNKNOWN 0xFF
-
+#ifndef ASICREV_IS_RAVEN
 #define ASICREV_IS_RAVEN(eChipRev) ((eChipRev >= RAVEN_A0) && eChipRev < RAVEN_UNKNOWN)
+#endif
+
 #define ASICREV_IS_PICASSO(eChipRev) ((eChipRev >= PICASSO_A0) && (eChipRev < RAVEN2_A0))
+#ifndef ASICREV_IS_RAVEN2
 #define ASICREV_IS_RAVEN2(eChipRev) ((eChipRev >= RAVEN2_A0) && (eChipRev < RAVEN1_F0))
+#endif
 #define ASICREV_IS_RV1_F0(eChipRev) ((eChipRev >= RAVEN1_F0) && (eChipRev < RAVEN_UNKNOWN))
 #define ASICREV_IS_DALI(eChipRev) ((eChipRev == RAVEN2_15D8_REV_E3) \
                || (eChipRev == RAVEN2_15D8_REV_E4))