dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks

Add #defines for Mobileye clock controller:

 - EyeQ5 core 0 thru 3 clocks. Internally:

      EQ5C_PLL_CPU:           already exposed
      └── EQ5C_CPU_OCC:       unexposed, no reason to do so
          ├── EQ5C_CPU_CORE0: new!
          ├── EQ5C_CPU_CORE1: new!
          ├── EQ5C_CPU_CORE2: new!
          └── EQ5C_CPU_CORE3: new!

 - EyeQ5 peripheral clocks. Internally:

      EQ5C_PLL_PER:          already exposed
      ├── EQ5C_PER_OCC:      new!
      │   ├── EQ5C_PER_SPI:  new!
      │   ├── EQ5C_PER_I2C:  new!
      │   ├── EQ5C_PER_GPIO: new!
      │   └── EQ5C_PER_UART: new!
      ├── EQ5C_PER_EMMC:     new!
      └── EQ5C_PER_OCC_PCI:  new!

 - EyeQ6H central OLB. Internally:

      EQ6HC_CENTRAL_PLL_CPU:     new!
      └── EQ6HC_CENTRAL_CPU_OCC: new!

 - EyeQ6H west OLB. Internally:

      EQ6HC_WEST_PLL_PER:          new!
      └── EQ6HC_WEST_PER_OCC:      new!
          └── EQ6HC_WEST_PER_UART: new!

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-2-84cfefb3f485@bootlin.com
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index b433c17..f353c29 100644 (file)
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -6,24 +6,46 @@
 #ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
 #define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
 
-#define EQ5C_PLL_CPU   0
-#define EQ5C_PLL_VMP   1
-#define EQ5C_PLL_PMA   2
-#define EQ5C_PLL_VDI   3
-#define EQ5C_PLL_DDR0  4
-#define EQ5C_PLL_PCI   5
-#define EQ5C_PLL_PER   6
-#define EQ5C_PLL_PMAC  7
-#define EQ5C_PLL_MPC   8
-#define EQ5C_PLL_DDR1  9
-
-#define EQ5C_DIV_OSPI  10
+#define EQ5C_PLL_CPU           0
+#define EQ5C_PLL_VMP           1
+#define EQ5C_PLL_PMA           2
+#define EQ5C_PLL_VDI           3
+#define EQ5C_PLL_DDR0          4
+#define EQ5C_PLL_PCI           5
+#define EQ5C_PLL_PER           6
+#define EQ5C_PLL_PMAC          7
+#define EQ5C_PLL_MPC           8
+#define EQ5C_PLL_DDR1          9
+
+#define EQ5C_DIV_OSPI          10
+
+/* EQ5C_PLL_CPU children */
+#define EQ5C_CPU_CORE0         11
+#define EQ5C_CPU_CORE1         12
+#define EQ5C_CPU_CORE2         13
+#define EQ5C_CPU_CORE3         14
+
+/* EQ5C_PLL_PER children */
+#define EQ5C_PER_OCC           15
+#define EQ5C_PER_UART          16
+#define EQ5C_PER_SPI           17
+#define EQ5C_PER_I2C           18
+#define EQ5C_PER_GPIO          19
+#define EQ5C_PER_EMMC          20
+#define EQ5C_PER_OCC_PCI       21
 
 #define EQ6LC_PLL_DDR          0
 #define EQ6LC_PLL_CPU          1
 #define EQ6LC_PLL_PER          2
 #define EQ6LC_PLL_VDI          3
 
+#define EQ6HC_CENTRAL_PLL_CPU  0
+#define EQ6HC_CENTRAL_CPU_OCC  1
+
+#define EQ6HC_WEST_PLL_PER     0
+#define EQ6HC_WEST_PER_OCC     1
+#define EQ6HC_WEST_PER_UART    2
+
 #define EQ6HC_SOUTH_PLL_VDI            0
 #define EQ6HC_SOUTH_PLL_PCIE           1
 #define EQ6HC_SOUTH_PLL_PER            2