ARM: dts: rockchip: Add display subsystem for RK3128

Add vop and display-subsystem nodes to RK3128's device tree.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
Link: https://lore.kernel.org/r/20231222174220.55249-28-knaerzche@gmail.com
Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi
index e2264c4..1a3bc8b 100644 (file)
--- a/arch/arm/boot/dts/rockchip/rk3128.dtsi
+++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi
@@ -115,6 +115,12 @@
                };
        };
 
+       display_subsystem: display-subsystem {
+               compatible = "rockchip,display-subsystem";
+               ports = <&vop_out>;
+               status = "disabled";
+       };
+
        gpu_opp_table: opp-table-1 {
                compatible = "operating-points-v2";
 
@@ -246,6 +252,27 @@
                };
        };
 
+       vop: vop@1010e000 {
+               compatible = "rockchip,rk3126-vop";
+               reg = <0x1010e000 0x300>;
+               interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
+               clocks = <&cru ACLK_LCDC0>, <&cru DCLK_VOP>,
+                        <&cru HCLK_LCDC0>;
+               clock-names = "aclk_vop", "dclk_vop",
+                             "hclk_vop";
+               resets = <&cru SRST_VOP_A>, <&cru SRST_VOP_H>,
+                        <&cru SRST_VOP_D>;
+               reset-names = "axi", "ahb",
+                             "dclk";
+               power-domains = <&power RK3128_PD_VIO>;
+               status = "disabled";
+
+               vop_out: port {
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+               };
+       };
+
        qos_gpu: qos@1012d000 {
                compatible = "rockchip,rk3128-qos", "syscon";
                reg = <0x1012d000 0x20>;