drm/amd/display: Read Sink emission rate capability

[WHY]
To get sink emission rate information for future
supported refresh rate calculation.

Reviewed-by: ChunTao Tso <chuntao.tso@amd.com>
Signed-off-by: Robin Chen <robin.chen@amd.com>
Signed-off-by: Roman Li <roman.li@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
index 50fa854..8dd6eb0 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
+++ b/drivers/gpu/drm/amd/display/dc/dc_dp_types.h
@@ -1192,6 +1192,7 @@ struct dpcd_caps {
        struct edp_psr_info psr_info;
 
        struct replay_info pr_info;
+       uint16_t edp_oled_emission_rate;
 };
 
 union dpcd_sink_ext_caps {
@@ -1205,7 +1206,7 @@ union dpcd_sink_ext_caps {
                uint8_t oled : 1;
                uint8_t reserved_2 : 1;
                uint8_t miniled : 1;
-               uint8_t reserved : 1;
+               uint8_t emission_output : 1;
        } bits;
        uint8_t raw;
 };

diff --git a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
index 2ec968f..952e787 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
+++ b/drivers/gpu/drm/amd/display/dc/link/protocols/link_dp_capability.c
@@ -2067,6 +2067,14 @@ void detect_edp_sink_caps(struct dc_link *link)
        core_link_read_dpcd(link, DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE,
                        &link->dpcd_caps.pr_info.max_deviation_line,
                        sizeof(link->dpcd_caps.pr_info.max_deviation_line));
+
+       /*
+        * OLED Emission Rate info
+        */
+       if (link->dpcd_sink_ext_caps.bits.emission_output)
+               core_link_read_dpcd(link, DP_SINK_EMISSION_RATE,
+                               (uint8_t *)&link->dpcd_caps.edp_oled_emission_rate,
+                               sizeof(link->dpcd_caps.edp_oled_emission_rate));
 }
 
 bool dp_get_max_link_enc_cap(const struct dc_link *link, struct dc_link_settings *max_link_enc_cap)

diff --git a/drivers/gpu/drm/amd/display/include/dpcd_defs.h b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
index aee5170..de8f3cf 100644 (file)
--- a/drivers/gpu/drm/amd/display/include/dpcd_defs.h
+++ b/drivers/gpu/drm/amd/display/include/dpcd_defs.h
@@ -164,18 +164,19 @@ enum dpcd_psr_sink_states {
        PSR_SINK_STATE_SINK_INTERNAL_ERROR = 7,
 };
 
-#define DP_SOURCE_SEQUENCE                 0x30c
-#define DP_SOURCE_TABLE_REVISION           0x310
-#define DP_SOURCE_PAYLOAD_SIZE             0x311
-#define DP_SOURCE_SINK_CAP                 0x317
-#define DP_SOURCE_BACKLIGHT_LEVEL          0x320
-#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK    0x326
-#define DP_SOURCE_BACKLIGHT_CONTROL        0x32E
-#define DP_SOURCE_BACKLIGHT_ENABLE         0x32F
-#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED     0x340
+#define DP_SOURCE_SEQUENCE                      0x30C
+#define DP_SOURCE_TABLE_REVISION                0x310
+#define DP_SOURCE_PAYLOAD_SIZE                  0x311
+#define DP_SOURCE_SINK_CAP                      0x317
+#define DP_SOURCE_BACKLIGHT_LEVEL               0x320
+#define DP_SOURCE_BACKLIGHT_CURRENT_PEAK        0x326
+#define DP_SOURCE_BACKLIGHT_CONTROL             0x32E
+#define DP_SOURCE_BACKLIGHT_ENABLE              0x32F
+#define DP_SOURCE_MINIMUM_HBLANK_SUPPORTED      0x340
 #define DP_SINK_PR_REPLAY_STATUS                0x378
 #define DP_SINK_PR_PIXEL_DEVIATION_PER_LINE     0x379
 #define DP_SINK_PR_MAX_NUMBER_OF_DEVIATION_LINE 0x37A
+#define DP_SINK_EMISSION_RATE                   0x37E
 
 /* Remove once drm_dp_helper.h is updated upstream */
 #ifndef DP_TOTAL_LTTPR_CNT