mt76: mt7915: add more statistics from fw_util debugfs knobs
authorRyder Lee <ryder.lee@mediatek.com>
Sun, 8 May 2022 05:24:54 +0000 (13:24 +0800)
committerFelix Fietkau <nbd@nbd.name>
Fri, 13 May 2022 07:39:35 +0000 (09:39 +0200)
Print out exception state and program counters of WA/WM MCUs.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Signed-off-by: Felix Fietkau <nbd@nbd.name>
drivers/net/wireless/mediatek/mt76/mt7915/debugfs.c
drivers/net/wireless/mediatek/mt76/mt7915/mmio.c
drivers/net/wireless/mediatek/mt76/mt7915/regs.h

index 11d1b2b..cab6e02 100644 (file)
@@ -597,6 +597,12 @@ mt7915_fw_util_wm_show(struct seq_file *file, void *data)
 {
        struct mt7915_dev *dev = file->private;
 
+       seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WM_MCU_PC));
+       seq_printf(file, "Exception state: 0x%x\n",
+                  is_mt7915(&dev->mt76) ?
+                  (u32)mt76_get_field(dev, MT_FW_EXCEPTION, GENMASK(15, 8)) :
+                  (u32)mt76_get_field(dev, MT_FW_EXCEPTION, GENMASK(7, 0)));
+
        if (dev->fw.debug_wm) {
                seq_printf(file, "Busy: %u%%  Peak busy: %u%%\n",
                           mt76_rr(dev, MT_CPU_UTIL_BUSY_PCT),
@@ -616,6 +622,8 @@ mt7915_fw_util_wa_show(struct seq_file *file, void *data)
 {
        struct mt7915_dev *dev = file->private;
 
+       seq_printf(file, "Program counter: 0x%x\n", mt76_rr(dev, MT_WA_MCU_PC));
+
        if (dev->fw.debug_wa)
                return mt7915_mcu_wa_cmd(dev, MCU_WA_PARAM_CMD(QUERY),
                                         MCU_WA_PARAM_CPU_UTIL, 0, 0);
index 846e710..46ee8a7 100644 (file)
@@ -22,6 +22,7 @@ static const u32 mt7915_reg[] = {
        [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
        [CBTOP1_PHY_END]        = 0x77ffffff,
        [INFRA_MCU_ADDR_END]    = 0x7c3fffff,
+       [FW_EXCEPTION_ADDR]     = 0x219848,
        [SWDEF_BASE_ADDR]       = 0x41f200,
 };
 
@@ -37,6 +38,7 @@ static const u32 mt7916_reg[] = {
        [WFDMA_EXT_CSR_ADDR]    = 0xd7000,
        [CBTOP1_PHY_END]        = 0x7fffffff,
        [INFRA_MCU_ADDR_END]    = 0x7c085fff,
+       [FW_EXCEPTION_ADDR]     = 0x022050bc,
        [SWDEF_BASE_ADDR]       = 0x411400,
 };
 
@@ -52,6 +54,7 @@ static const u32 mt7986_reg[] = {
        [WFDMA_EXT_CSR_ADDR]    = 0x27000,
        [CBTOP1_PHY_END]        = 0x7fffffff,
        [INFRA_MCU_ADDR_END]    = 0x7c085fff,
+       [FW_EXCEPTION_ADDR]     = 0x02204ffc,
        [SWDEF_BASE_ADDR]       = 0x411400,
 };
 
index 31dffb9..4953be2 100644 (file)
@@ -30,6 +30,7 @@ enum reg_rev {
        WFDMA_EXT_CSR_ADDR,
        CBTOP1_PHY_END,
        INFRA_MCU_ADDR_END,
+       FW_EXCEPTION_ADDR,
        SWDEF_BASE_ADDR,
        __MT_REG_MAX,
 };
@@ -939,6 +940,8 @@ enum offs_rev {
 #define MT_ADIE_TYPE_MASK              BIT(1)
 
 /* FW MODE SYNC */
+#define MT_FW_EXCEPTION                __REG(FW_EXCEPTION_ADDR)
+
 #define MT_SWDEF_BASE                  __REG(SWDEF_BASE_ADDR)
 
 #define MT_SWDEF(ofs)                  (MT_SWDEF_BASE + (ofs))
@@ -1004,10 +1007,6 @@ enum offs_rev {
 #define MT_TOP_MISC                    MT_TOP(0xf0)
 #define MT_TOP_MISC_FW_STATE           GENMASK(2, 0)
 
-#define MT_HW_BOUND                    0x70010020
-#define MT_HW_REV                      0x70010204
-#define MT_WF_SUBSYS_RST               0x70002600
-
 #define MT_TOP_WFSYS_WAKEUP            MT_TOP(0x1a4)
 #define MT_TOP_WFSYS_WAKEUP_MASK       BIT(0)
 
@@ -1069,6 +1068,10 @@ enum offs_rev {
 #define MT_MCU_BUS_DBG_TIMEOUT_CK_EN_MASK BIT(3)
 #define MT_MCU_BUS_DBG_TIMEOUT_EN_MASK BIT(2)
 
+#define MT_HW_BOUND                    0x70010020
+#define MT_HW_REV                      0x70010204
+#define MT_WF_SUBSYS_RST               0x70002600
+
 /* PCIE MAC */
 #define MT_PCIE_MAC_BASE               0x74030000
 #define MT_PCIE_MAC(ofs)               (MT_PCIE_MAC_BASE + (ofs))
@@ -1077,6 +1080,9 @@ enum offs_rev {
 #define MT_PCIE1_MAC_INT_ENABLE                0x74020188
 #define MT_PCIE1_MAC_INT_ENABLE_MT7916 0x74090188
 
+#define MT_WM_MCU_PC                   0x7c060204
+#define MT_WA_MCU_PC                   0x7c06020c
+
 /* PP TOP */
 #define MT_WF_PP_TOP_BASE              0x820cc000
 #define MT_WF_PP_TOP(ofs)              (MT_WF_PP_TOP_BASE + (ofs))