int prev_disp_clk = core_dc->current_context->dispclk_khz;
struct dc_stream_status *stream_status = NULL;
struct validate_context *context;
- struct validate_context *temp_context;
bool ret = true;
pre_surface_trace(dc, new_surfaces, new_surface_count);
if (update_type == UPDATE_TYPE_FULL) {
for (j = 0; j < context->res_ctx.pool->pipe_count; j++) {
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[j];
- struct core_stream *stream = pipe_ctx->stream;
if (pipe_ctx->surface != surface)
continue;
const struct dc_surface *dc_surface)
{
struct dc_surface_status *surface_status;
- struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);;
+ struct core_surface *core_surface = DC_SURFACE_TO_CORE(dc_surface);
struct core_dc *core_dc;
int i;
static bool dce_abm_set_level(struct abm *abm, uint32_t level)
{
struct dce_abm *abm_dce = TO_DCE_ABM(abm);
- struct dc_context *ctx = abm_dce->base.ctx;
REG_WAIT(MASTER_COMM_CNTL_REG, MASTER_COMM_INTERRUPT, 0,
100, 800);
static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg)
{
- struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg);
uint32_t addr = mmCRTCV_BLANK_CONTROL;
uint32_t value = dm_read_reg(tg->ctx, addr);