drm/i915/icl: Switch to using 12 deep CSB status FIFO

Now when we can support variable csb fifo sizes, disable legacy mode.
By disabling legacy we hope to get better hw testing coverage by
assuming everyone else have switched over.

v2: rebase

References: https://bugs.freedesktop.org/show_bug.cgi?id=110338
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Kelvin Gardiner <kelvin.gardiner@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20190405204657.12887-2-chris@chris-wilson.co.uk

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 6a104ce..75446e4 100644 (file)
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1849,17 +1849,9 @@ static void enable_execlists(struct intel_engine_cs *engine)
 
        intel_engine_set_hwsp_writemask(engine, ~0u); /* HWSTAM */
 
-       /*
-        * Make sure we're not enabling the new 12-deep CSB
-        * FIFO as that requires a slightly updated handling
-        * in the ctx switch irq. Since we're currently only
-        * using only 2 elements of the enhanced execlists the
-        * deeper FIFO it's not needed and it's not worth adding
-        * more statements to the irq handler to support it.
-        */
        if (INTEL_GEN(dev_priv) >= 11)
                I915_WRITE(RING_MODE_GEN7(engine),
-                          _MASKED_BIT_DISABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
+                          _MASKED_BIT_ENABLE(GEN11_GFX_DISABLE_LEGACY_MODE));
        else
                I915_WRITE(RING_MODE_GEN7(engine),
                           _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE));
@@ -2477,7 +2469,10 @@ static int logical_ring_init(struct intel_engine_cs *engine)
        execlists->csb_write =
                &engine->status_page.addr[intel_hws_csb_write_index(i915)];
 
-       execlists->csb_size = GEN8_CSB_ENTRIES;
+       if (INTEL_GEN(engine->i915) < 11)
+               execlists->csb_size = GEN8_CSB_ENTRIES;
+       else
+               execlists->csb_size = GEN11_CSB_ENTRIES;
 
        reset_csb_pointers(execlists);