drm/amd/powerplay: update UMD pstate clock settings

Preparing for coming code sharing around performance level
setting.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
index 39126e2..ff35dce 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
+++ b/drivers/gpu/drm/amd/powerplay/amdgpu_smu.c
@@ -2168,6 +2168,8 @@ int smu_read_sensor(struct smu_context *smu,
                    enum amd_pp_sensors sensor,
                    void *data, uint32_t *size)
 {
+       struct smu_umd_pstate_table *pstate_table =
+                               &smu->pstate_table;
        int ret = 0;
 
        if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
@@ -2180,11 +2182,11 @@ int smu_read_sensor(struct smu_context *smu,
 
        switch (sensor) {
        case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
-               *((uint32_t *)data) = smu->pstate_sclk;
+               *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
                *size = 4;
                break;
        case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
-               *((uint32_t *)data) = smu->pstate_mclk;
+               *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
                *size = 4;
                break;
        case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:

diff --git a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
index a3747ab..33d472f 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/arcturus_ppt.c
@@ -548,27 +548,44 @@ static int arcturus_run_btc(struct smu_context *smu)
 
 static int arcturus_populate_umd_state_clk(struct smu_context *smu)
 {
-       struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
-       struct arcturus_dpm_table *dpm_table = NULL;
-       struct arcturus_single_dpm_table *gfx_table = NULL;
-       struct arcturus_single_dpm_table *mem_table = NULL;
+       struct smu_11_0_dpm_context *dpm_context =
+                               smu->smu_dpm.dpm_context;
+       struct smu_11_0_dpm_table *gfx_table =
+                               &dpm_context->dpm_tables.gfx_table;
+       struct smu_11_0_dpm_table *mem_table =
+                               &dpm_context->dpm_tables.uclk_table;
+       struct smu_11_0_dpm_table *soc_table =
+                               &dpm_context->dpm_tables.soc_table;
+       struct smu_umd_pstate_table *pstate_table =
+                               &smu->pstate_table;
+
+       pstate_table->gfxclk_pstate.min = gfx_table->min;
+       pstate_table->gfxclk_pstate.peak = gfx_table->max;
 
-       dpm_table = smu_dpm->dpm_context;
-       gfx_table = &(dpm_table->gfx_table);
-       mem_table = &(dpm_table->mem_table);
+       pstate_table->uclk_pstate.min = mem_table->min;
+       pstate_table->uclk_pstate.peak = mem_table->max;
 
-       smu->pstate_sclk = gfx_table->dpm_levels[0].value;
-       smu->pstate_mclk = mem_table->dpm_levels[0].value;
+       pstate_table->socclk_pstate.min = soc_table->min;
+       pstate_table->socclk_pstate.peak = soc_table->max;
 
        if (gfx_table->count > ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL &&
-           mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL) {
-               smu->pstate_sclk = gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
-               smu->pstate_mclk = mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+           mem_table->count > ARCTURUS_UMD_PSTATE_MCLK_LEVEL &&
+           soc_table->count > ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL) {
+               pstate_table->gfxclk_pstate.standard =
+                       gfx_table->dpm_levels[ARCTURUS_UMD_PSTATE_GFXCLK_LEVEL].value;
+               pstate_table->uclk_pstate.standard =
+                       mem_table->dpm_levels[ARCTURUS_UMD_PSTATE_MCLK_LEVEL].value;
+               pstate_table->socclk_pstate.standard =
+                       soc_table->dpm_levels[ARCTURUS_UMD_PSTATE_SOCCLK_LEVEL].value;
+       } else {
+               pstate_table->gfxclk_pstate.standard =
+                       pstate_table->gfxclk_pstate.min;
+               pstate_table->uclk_pstate.standard =
+                       pstate_table->uclk_pstate.min;
+               pstate_table->socclk_pstate.standard =
+                       pstate_table->socclk_pstate.min;
        }
 
-       smu->pstate_sclk = smu->pstate_sclk * 100;
-       smu->pstate_mclk = smu->pstate_mclk * 100;
-
        return 0;
 }
 

diff --git a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
index e3b1410..ddf9a92 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/navi10_ppt.c
@@ -1213,22 +1213,93 @@ static int navi10_force_clk_levels(struct smu_context *smu,
 
 static int navi10_populate_umd_state_clk(struct smu_context *smu)
 {
-       int ret = 0;
-       uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
-
-       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
-       if (ret)
-               return ret;
-
-       smu->pstate_sclk = min_sclk_freq * 100;
-
-       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
-       if (ret)
-               return ret;
+       struct smu_11_0_dpm_context *dpm_context =
+                               smu->smu_dpm.dpm_context;
+       struct smu_11_0_dpm_table *gfx_table =
+                               &dpm_context->dpm_tables.gfx_table;
+       struct smu_11_0_dpm_table *mem_table =
+                               &dpm_context->dpm_tables.uclk_table;
+       struct smu_11_0_dpm_table *soc_table =
+                               &dpm_context->dpm_tables.soc_table;
+       struct smu_umd_pstate_table *pstate_table =
+                               &smu->pstate_table;
+       struct amdgpu_device *adev = smu->adev;
+       uint32_t sclk_freq;
 
-       smu->pstate_mclk = min_mclk_freq * 100;
+       pstate_table->gfxclk_pstate.min = gfx_table->min;
+       switch (adev->asic_type) {
+       case CHIP_NAVI10:
+               switch (adev->pdev->revision) {
+               case 0xf0: /* XTX */
+               case 0xc0:
+                       sclk_freq = NAVI10_PEAK_SCLK_XTX;
+                       break;
+               case 0xf1: /* XT */
+               case 0xc1:
+                       sclk_freq = NAVI10_PEAK_SCLK_XT;
+                       break;
+               default: /* XL */
+                       sclk_freq = NAVI10_PEAK_SCLK_XL;
+                       break;
+               }
+               break;
+       case CHIP_NAVI14:
+               switch (adev->pdev->revision) {
+               case 0xc7: /* XT */
+               case 0xf4:
+                       sclk_freq = NAVI14_UMD_PSTATE_PEAK_XT_GFXCLK;
+                       break;
+               case 0xc1: /* XTM */
+               case 0xf2:
+                       sclk_freq = NAVI14_UMD_PSTATE_PEAK_XTM_GFXCLK;
+                       break;
+               case 0xc3: /* XLM */
+               case 0xf3:
+                       sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
+                       break;
+               case 0xc5: /* XTX */
+               case 0xf6:
+                       sclk_freq = NAVI14_UMD_PSTATE_PEAK_XLM_GFXCLK;
+                       break;
+               default: /* XL */
+                       sclk_freq = NAVI14_UMD_PSTATE_PEAK_XL_GFXCLK;
+                       break;
+               }
+               break;
+       case CHIP_NAVI12:
+               sclk_freq = NAVI12_UMD_PSTATE_PEAK_GFXCLK;
+               break;
+       default:
+               sclk_freq = gfx_table->dpm_levels[gfx_table->count - 1].value;
+               break;
+       }
+       pstate_table->gfxclk_pstate.peak = sclk_freq;
+
+       pstate_table->uclk_pstate.min = mem_table->min;
+       pstate_table->uclk_pstate.peak = mem_table->max;
+
+       pstate_table->socclk_pstate.min = soc_table->min;
+       pstate_table->socclk_pstate.peak = soc_table->max;
+
+       if (gfx_table->max > NAVI10_UMD_PSTATE_PROFILING_GFXCLK &&
+           mem_table->max > NAVI10_UMD_PSTATE_PROFILING_MEMCLK &&
+           soc_table->max > NAVI10_UMD_PSTATE_PROFILING_SOCCLK) {
+               pstate_table->gfxclk_pstate.standard =
+                       NAVI10_UMD_PSTATE_PROFILING_GFXCLK;
+               pstate_table->uclk_pstate.standard =
+                       NAVI10_UMD_PSTATE_PROFILING_MEMCLK;
+               pstate_table->socclk_pstate.standard =
+                       NAVI10_UMD_PSTATE_PROFILING_SOCCLK;
+       } else {
+               pstate_table->gfxclk_pstate.standard =
+                       pstate_table->gfxclk_pstate.min;
+               pstate_table->uclk_pstate.standard =
+                       pstate_table->uclk_pstate.min;
+               pstate_table->socclk_pstate.standard =
+                       pstate_table->socclk_pstate.min;
+       }
 
-       return ret;
+       return 0;
 }
 
 static int navi10_get_clock_by_type_with_latency(struct smu_context *smu,

diff --git a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
index 23dbf7f..beffb9d 100644 (file)
--- a/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
+++ b/drivers/gpu/drm/amd/powerplay/sienna_cichlid_ppt.c
@@ -1115,22 +1115,27 @@ forec_level_out:
 
 static int sienna_cichlid_populate_umd_state_clk(struct smu_context *smu)
 {
-       int ret = 0;
-       uint32_t min_sclk_freq = 0, min_mclk_freq = 0;
-
-       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_SCLK, &min_sclk_freq, NULL);
-       if (ret)
-               return ret;
-
-       smu->pstate_sclk = min_sclk_freq * 100;
+       struct smu_11_0_dpm_context *dpm_context =
+                               smu->smu_dpm.dpm_context;
+       struct smu_11_0_dpm_table *gfx_table =
+                               &dpm_context->dpm_tables.gfx_table;
+       struct smu_11_0_dpm_table *mem_table =
+                               &dpm_context->dpm_tables.uclk_table;
+       struct smu_11_0_dpm_table *soc_table =
+                               &dpm_context->dpm_tables.soc_table;
+       struct smu_umd_pstate_table *pstate_table =
+                               &smu->pstate_table;
+
+       pstate_table->gfxclk_pstate.min = gfx_table->min;
+       pstate_table->gfxclk_pstate.peak = gfx_table->max;
+
+       pstate_table->uclk_pstate.min = mem_table->min;
+       pstate_table->uclk_pstate.peak = mem_table->max;
+
+       pstate_table->socclk_pstate.min = soc_table->min;
+       pstate_table->socclk_pstate.peak = soc_table->max;
 
-       ret = smu_v11_0_get_dpm_ultimate_freq(smu, SMU_MCLK, &min_mclk_freq, NULL);
-       if (ret)
-               return ret;
-
-       smu->pstate_mclk = min_mclk_freq * 100;
-
-       return ret;
+       return 0;
 }
 
 static int sienna_cichlid_pre_display_config_changed(struct smu_context *smu)