arm64: dts: qcom: sm8450: Add rpmhpd node

This adds RPMH power domain found in SM8450 SoC

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/20211215043440.605624-10-vkoul@kernel.org

diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi
index 9556d2f..8fff4d5 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sm8450.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi
@@ -7,6 +7,7 @@
 #include <dt-bindings/clock/qcom,gcc-sm8450.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/power/qcom-rpmpd.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
 
 / {
@@ -814,6 +815,56 @@
                                clock-names = "xo";
                                clocks = <&xo_board>;
                        };
+
+                       rpmhpd: power-controller {
+                               compatible = "qcom,sm8450-rpmhpd";
+                               #power-domain-cells = <1>;
+                               operating-points-v2 = <&rpmhpd_opp_table>;
+
+                               rpmhpd_opp_table: opp-table {
+                                       compatible = "operating-points-v2";
+
+                                       rpmhpd_opp_ret: opp1 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>;
+                                       };
+
+                                       rpmhpd_opp_min_svs: opp2 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
+                                       };
+
+                                       rpmhpd_opp_low_svs: opp3 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
+                                       };
+
+                                       rpmhpd_opp_svs: opp4 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
+                                       };
+
+                                       rpmhpd_opp_svs_l1: opp5 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
+                                       };
+
+                                       rpmhpd_opp_nom: opp6 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
+                                       };
+
+                                       rpmhpd_opp_nom_l1: opp7 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+                                       };
+
+                                       rpmhpd_opp_nom_l2: opp8 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>;
+                                       };
+
+                                       rpmhpd_opp_turbo: opp9 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
+                                       };
+
+                                       rpmhpd_opp_turbo_l1: opp10 {
+                                               opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+                                       };
+                               };
+                       };
                };
 
                ufs_mem_hc: ufshc@1d84000 {