drm/xe: Drop __engine_mask

Not really used, it's just a copy of engine_mask, which already reads
the fuses to mark engines as available/not-available.

Reviewed-by: Michał Winiarski <michal.winiarski@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20240513213751.1017791-1-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>

diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 36c7b16..3b3418e 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -518,9 +518,6 @@ int xe_gt_init_hwconfig(struct xe_gt *gt)
        if (err)
                goto out_fw;
 
-       /* XXX: Fake that we pull the engine mask from hwconfig blob */
-       gt->info.engine_mask = gt->info.__engine_mask;
-
 out_fw:
        xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
 out:

diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
index 8dc2034..5a114fc 100644 (file)
--- a/drivers/gpu/drm/xe/xe_gt_types.h
+++ b/drivers/gpu/drm/xe/xe_gt_types.h
@@ -114,12 +114,6 @@ struct xe_gt {
                u32 reference_clock;
                /** @info.engine_mask: mask of engines present on GT */
                u64 engine_mask;
-               /**
-                * @info.__engine_mask: mask of engines present on GT read from
-                * xe_pci.c, used to fake reading the engine_mask from the
-                * hwconfig blob.
-                */
-               u64 __engine_mask;
                /** @info.gmdid: raw GMD_ID value from hardware */
                u32 gmdid;
                /** @info.id: Unique ID of this GT within the PCI Device */

diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
index 36db5ed..2b12f36 100644 (file)
--- a/drivers/gpu/drm/xe/xe_migrate.c
+++ b/drivers/gpu/drm/xe/xe_migrate.c
@@ -936,8 +936,8 @@ static bool has_service_copy_support(struct xe_gt *gt)
         * all of the actual service copy engines (BCS1-BCS8) have been fused
         * off.
         */
-       return gt->info.__engine_mask & GENMASK(XE_HW_ENGINE_BCS8,
-                                               XE_HW_ENGINE_BCS1);
+       return gt->info.engine_mask & GENMASK(XE_HW_ENGINE_BCS8,
+                                             XE_HW_ENGINE_BCS1);
 }
 
 static u32 emit_clear_cmd_len(struct xe_gt *gt)

diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
index 83e662a..fc29eb8 100644 (file)
--- a/drivers/gpu/drm/xe/xe_pci.c
+++ b/drivers/gpu/drm/xe/xe_pci.c
@@ -663,9 +663,9 @@ static int xe_info_init(struct xe_device *xe,
                gt->info.id = xe->info.gt_count++;
                gt->info.type = XE_GT_TYPE_MAIN;
                gt->info.has_indirect_ring_state = graphics_desc->has_indirect_ring_state;
-               gt->info.__engine_mask = graphics_desc->hw_engine_mask;
+               gt->info.engine_mask = graphics_desc->hw_engine_mask;
                if (MEDIA_VER(xe) < 13 && media_desc)
-                       gt->info.__engine_mask |= media_desc->hw_engine_mask;
+                       gt->info.engine_mask |= media_desc->hw_engine_mask;
 
                if (MEDIA_VER(xe) < 13 || !media_desc)
                        continue;
@@ -681,7 +681,7 @@ static int xe_info_init(struct xe_device *xe,
                gt = tile->media_gt;
                gt->info.type = XE_GT_TYPE_MEDIA;
                gt->info.has_indirect_ring_state = media_desc->has_indirect_ring_state;
-               gt->info.__engine_mask = media_desc->hw_engine_mask;
+               gt->info.engine_mask = media_desc->hw_engine_mask;
                gt->mmio.adj_offset = MEDIA_GT_GSI_OFFSET;
                gt->mmio.adj_limit = MEDIA_GT_GSI_LENGTH;