drm/i915: Introduce new macros for i915 PTE

Certain functions within i915 uses macros that are defined for
specific architectures by the mmu, such as _PAGE_RW and _PAGE_PRESENT
(Some architectures don't even have these macros defined, like ARM64).

Instead of re-using bits defined for the CPU, we should use bits
defined for i915. This patch introduces two new 64 bit macros,
GEN8_PAGE_PRESENT and GEN8_PAGE_RW, to check for bits 0 and 1 and, to
replace all occurrences of _PAGE_RW and _PAGE_PRESENT within i915.

v2(Michael Cheng): Use GEN8_ instead of I915_

Signed-off-by: Michael Cheng <michael.cheng@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
[ Move defines together with other GEN8 defines ]
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20211206215245.513677-2-michael.cheng@intel.com

diff --git a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
index 9966e9d..95c0209 100644 (file)
--- a/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
+++ b/drivers/gpu/drm/i915/gt/gen8_ppgtt.c
@@ -18,7 +18,7 @@
 static u64 gen8_pde_encode(const dma_addr_t addr,
                           const enum i915_cache_level level)
 {
-       u64 pde = addr | _PAGE_PRESENT | _PAGE_RW;
+       u64 pde = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
 
        if (level != I915_CACHE_NONE)
                pde |= PPAT_CACHED_PDE;
@@ -32,10 +32,10 @@ static u64 gen8_pte_encode(dma_addr_t addr,
                           enum i915_cache_level level,
                           u32 flags)
 {
-       gen8_pte_t pte = addr | _PAGE_PRESENT | _PAGE_RW;
+       gen8_pte_t pte = addr | GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
 
        if (unlikely(flags & PTE_READ_ONLY))
-               pte &= ~_PAGE_RW;
+               pte &= ~GEN8_PAGE_RW;
 
        if (flags & PTE_LM)
                pte |= GEN12_PPGTT_PTE_LM;

diff --git a/drivers/gpu/drm/i915/gt/intel_ggtt.c b/drivers/gpu/drm/i915/gt/intel_ggtt.c
index b943f20..7a85d65 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_ggtt.c
+++ b/drivers/gpu/drm/i915/gt/intel_ggtt.c
@@ -192,7 +192,7 @@ u64 gen8_ggtt_pte_encode(dma_addr_t addr,
                         enum i915_cache_level level,
                         u32 flags)
 {
-       gen8_pte_t pte = addr | _PAGE_PRESENT;
+       gen8_pte_t pte = addr | GEN8_PAGE_PRESENT;
 
        if (flags & PTE_LM)
                pte |= GEN12_GGTT_PTE_LM;

diff --git a/drivers/gpu/drm/i915/gt/intel_gtt.h b/drivers/gpu/drm/i915/gt/intel_gtt.h
index bc67502..d8377ed 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_gtt.h
+++ b/drivers/gpu/drm/i915/gt/intel_gtt.h
@@ -135,6 +135,9 @@ typedef u64 gen8_pte_t;
 #define GEN8_PPAT_ELLC_OVERRIDE                (0<<2)
 #define GEN8_PPAT(i, x)                        ((u64)(x) << ((i) * 8))
 
+#define GEN8_PAGE_PRESENT              BIT_ULL(0)
+#define GEN8_PAGE_RW                   BIT_ULL(1)
+
 #define GEN8_PDE_IPS_64K BIT(11)
 #define GEN8_PDE_PS_2M   BIT(7)
 

diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index 53d0cb3..99d1781 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -446,17 +446,17 @@ static bool gen8_gtt_test_present(struct intel_gvt_gtt_entry *e)
                        || e->type == GTT_TYPE_PPGTT_ROOT_L4_ENTRY)
                return (e->val64 != 0);
        else
-               return (e->val64 & _PAGE_PRESENT);
+               return (e->val64 & GEN8_PAGE_PRESENT);
 }
 
 static void gtt_entry_clear_present(struct intel_gvt_gtt_entry *e)
 {
-       e->val64 &= ~_PAGE_PRESENT;
+       e->val64 &= ~GEN8_PAGE_PRESENT;
 }
 
 static void gtt_entry_set_present(struct intel_gvt_gtt_entry *e)
 {
-       e->val64 |= _PAGE_PRESENT;
+       e->val64 |= GEN8_PAGE_PRESENT;
 }
 
 static bool gen8_gtt_test_64k_splited(struct intel_gvt_gtt_entry *e)
@@ -2439,7 +2439,7 @@ static int alloc_scratch_pages(struct intel_vgpu *vgpu,
                /* The entry parameters like present/writeable/cache type
                 * set to the same as i915's scratch page tree.
                 */
-               se.val64 |= _PAGE_PRESENT | _PAGE_RW;
+               se.val64 |= GEN8_PAGE_PRESENT | GEN8_PAGE_RW;
                if (type == GTT_TYPE_PPGTT_PDE_PT)
                        se.val64 |= PPAT_CACHED;
 
@@ -2896,7 +2896,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
                offset = vgpu_aperture_gmadr_base(vgpu) >> PAGE_SHIFT;
                for (idx = 0; idx < num_low; idx++) {
                        pte = mm->ggtt_mm.host_ggtt_aperture[idx];
-                       if (pte & _PAGE_PRESENT)
+                       if (pte & GEN8_PAGE_PRESENT)
                                write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
                }
 
@@ -2904,7 +2904,7 @@ void intel_gvt_restore_ggtt(struct intel_gvt *gvt)
                offset = vgpu_hidden_gmadr_base(vgpu) >> PAGE_SHIFT;
                for (idx = 0; idx < num_hi; idx++) {
                        pte = mm->ggtt_mm.host_ggtt_hidden[idx];
-                       if (pte & _PAGE_PRESENT)
+                       if (pte & GEN8_PAGE_PRESENT)
                                write_pte64(vgpu->gvt->gt->ggtt, offset + idx, pte);
                }
        }