staging: rtl8192u: fix comments in r819xU_phy.c
authorXenia Ragiadakou <burzalodowa@gmail.com>
Wed, 19 Jun 2013 01:58:07 +0000 (04:58 +0300)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 19 Jun 2013 16:41:40 +0000 (09:41 -0700)
This patch fixes the comments in r819xU_phy.c by:
- replacing "// ..." with "/* .... */"
- removing unnecessary comments, the dates and names of
  developers from comments
- fixing some inconsistent comments
- fixing some typos
- fixing alignment issues

Signed-off-by: Xenia Ragiadakou <burzalodowa@gmail.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/staging/rtl8192u/r819xU_phy.c

index 9bfcd2f..627165a 100644 (file)
 
 static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
        0,
-       0x085c, //2412 1
-       0x08dc, //2417 2
-       0x095c, //2422 3
-       0x09dc, //2427 4
-       0x0a5c, //2432 5
-       0x0adc, //2437 6
-       0x0b5c, //2442 7
-       0x0bdc, //2447 8
-       0x0c5c, //2452 9
-       0x0cdc, //2457 10
-       0x0d5c, //2462 11
-       0x0ddc, //2467 12
-       0x0e5c, //2472 13
-       0x0f72, //2484
+       0x085c, /* 2412 1  */
+       0x08dc, /* 2417 2  */
+       0x095c, /* 2422 3  */
+       0x09dc, /* 2427 4  */
+       0x0a5c, /* 2432 5  */
+       0x0adc, /* 2437 6  */
+       0x0b5c, /* 2442 7  */
+       0x0bdc, /* 2447 8  */
+       0x0c5c, /* 2452 9  */
+       0x0cdc, /* 2457 10 */
+       0x0d5c, /* 2462 11 */
+       0x0ddc, /* 2467 12 */
+       0x0e5c, /* 2472 13 */
+       0x0f72, /* 2484    */
 };
 
 
@@ -38,12 +38,12 @@ static u32 RF_CHANNEL_TABLE_ZEBRA[] = {
 #define rtl819XAGCTAB_Array Rtl8192UsbAGCTAB_Array
 
 /******************************************************************************
- *function:  This function read BB parameters from Header file we gen,
- *          and do register read/write
- *   input:  u32       bitmask  //taget bit pos in the addr to be modified
- *  output:  none
- *  return:  u32       return the shift bit position of the mask
- * ****************************************************************************/
+ * function: This function reads BB parameters from header file we generate,
+ *           and does register read/write
+ * input:    u32       bitmask  //taget bit pos in the addr to be modified
+ * output:   none
+ * return:   u32       return the shift bit position of the mask
+ ******************************************************************************/
 u32 rtl8192_CalculateBitShift(u32 bitmask)
 {
        u32 i;
@@ -51,11 +51,13 @@ u32 rtl8192_CalculateBitShift(u32 bitmask)
        return i;
 }
 /******************************************************************************
- *function:  This function check different RF type to execute legal judgement. If RF Path is illegal, we will return false.
- *   input:  none
- *  output:  none
- *  return:  0(illegal, false), 1(legal,true)
- * ***************************************************************************/
+ * function:  This function checks different RF type to execute legal judgement.
+ *            If RF Path is illegal, we will return false.
+ * input:     net_device        *dev
+ *            u32               eRFPath
+ * output:    none
+ * return:    0(illegal, false), 1(legal, true)
+ *****************************************************************************/
 u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
 {
        u8 ret = 1;
@@ -71,22 +73,22 @@ u8 rtl8192_phy_CheckIsLegalRFPath(struct net_device *dev, u32 eRFPath)
        return ret;
 }
 /******************************************************************************
- *function:  This function set specific bits to BB register
- *   input:  net_device dev
- *           u32       reg_addr   //target addr to be modified
- *           u32       bitmask    //taget bit pos in the addr to be modified
- *           u32       data       //value to be write
- *  output:  none
- *  return:  none
- *  notice:
- * ****************************************************************************/
+ * function:  This function sets specific bits to BB register
+ * input:     net_device *dev
+ *            u32        reg_addr   //target addr to be modified
+ *            u32        bitmask    //taget bit pos to be modified
+ *            u32        data       //value to be write
+ * output:    none
+ * return:    none
+ * notice:
+ ******************************************************************************/
 void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
                      u32 data)
 {
 
        u32 reg, bitshift;
 
-       if (bitmask != bMaskDWord) { //if not "double word" write
+       if (bitmask != bMaskDWord) {
                read_nic_dword(dev, reg_addr, &reg);
                bitshift = rtl8192_CalculateBitShift(bitmask);
                reg &= ~bitmask;
@@ -98,14 +100,14 @@ void rtl8192_setBBreg(struct net_device *dev, u32 reg_addr, u32 bitmask,
        return;
 }
 /******************************************************************************
- *function:  This function reads specific bits from BB register
- *   input:  net_device dev
- *           u32       reg_addr   //target addr to be readback
- *           u32       bitmask    //taget bit pos in the addr to be readback
- *  output:  none
- *  return:  u32       data       //the readback register value
- *  notice:
- * ****************************************************************************/
+ * function:  This function reads specific bits from BB register
+ * input:     net_device       *dev
+ *            u32              reg_addr   //target addr to be readback
+ *            u32              bitmask    //taget bit pos to be readback
+ * output:    none
+ * return:    u32              data       //the readback register value
+ * notice:
+ ******************************************************************************/
 u32 rtl8192_QueryBBReg(struct net_device *dev, u32 reg_addr, u32 bitmask)
 {
        u32 reg, bitshift;
@@ -123,14 +125,19 @@ static void phy_FwRFSerialWrite(struct net_device *dev,
                                u32  data);
 
 /******************************************************************************
- *function:  This function read register from RF chip
- *   input:  net_device dev
- *          RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
- *           u32       offset     //target address to be read
- *  output:  none
- *  return:  u32       readback value
- *  notice:  There are three types of serial operations:(1) Software serial write.(2)Hardware LSSI-Low Speed Serial Interface.(3)Hardware HSSI-High speed serial write. Driver here need to implement (1) and (2)---need more spec for this information.
- * ****************************************************************************/
+ * function:  This function reads register from RF chip
+ * input:     net_device        *dev
+ *            RF90_RADIO_PATH_E eRFPath    //radio path of A/B/C/D
+ *            u32               offset     //target address to be read
+ * output:    none
+ * return:    u32               readback value
+ * notice:    There are three types of serial operations:
+ *            (1) Software serial write.
+ *            (2)Hardware LSSI-Low Speed Serial Interface.
+ *            (3)Hardware HSSI-High speed serial write.
+ *            Driver here need to implement (1) and (2)
+ *            ---need more spec for this information.
+ ******************************************************************************/
 u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                             u32 offset)
 {
@@ -139,21 +146,21 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
        u32 new_offset = 0;
        BB_REGISTER_DEFINITION_T *pPhyReg = &priv->PHYRegDef[eRFPath];
        rtl8192_setBBreg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData, 0);
-       //make sure RF register offset is correct
+       /* Make sure RF register offset is correct */
        offset &= 0x3f;
 
-       //switch page for 8256 RF IC
+       /* Switch page for 8256 RF IC */
        if (priv->rf_chip == RF_8256) {
                if (offset >= 31) {
                        priv->RfReg0Value[eRFPath] |= 0x140;
-                       //Switch to Reg_Mode2 for Reg 31-45
+                       /* Switch to Reg_Mode2 for Reg 31-45 */
                        rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
-                       //modify offset
+                       /* Modify offset */
                        new_offset = offset - 30;
                } else if (offset >= 16) {
                        priv->RfReg0Value[eRFPath] |= 0x100;
                        priv->RfReg0Value[eRFPath] &= (~0x40);
-                       //Switch to Reg_Mode 1 for Reg16-30
+                       /* Switch to Reg_Mode1 for Reg16-30 */
                        rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, (priv->RfReg0Value[eRFPath]<<16));
 
                        new_offset = offset - 15;
@@ -164,21 +171,20 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                RT_TRACE((COMP_PHY|COMP_ERR), "check RF type here, need to be 8256\n");
                new_offset = offset;
        }
-       //put desired read addr to LSSI control Register
+       /* Put desired read addr to LSSI control Register */
        rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, bLSSIReadAddress, new_offset);
-       //Issue a posedge trigger
-       //
+       /* Issue a posedge trigger */
        rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x0);
        rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2,  bLSSIReadEdge, 0x1);
 
 
-       // TODO: we should not delay such a long time. Ask for help from SD3
+       /* TODO: we should not delay such a long time. Ask for help from SD3 */
        msleep(1);
 
        ret = rtl8192_QueryBBReg(dev, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 
 
-       // Switch back to Reg_Mode0;
+       /* Switch back to Reg_Mode0 */
        if (priv->rf_chip == RF_8256) {
                priv->RfReg0Value[eRFPath] &= 0xebf;
 
@@ -194,25 +200,25 @@ u32 rtl8192_phy_RFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 }
 
 /******************************************************************************
- *function:  This function write data to RF register
- *   input:  net_device dev
- *          RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
- *           u32       offset     //target address to be written
- *           u32       data       //The new register data to be written
- *  output:  none
- *  return:  none
- *  notice:  For RF8256 only.
 ===========================================================
- *Reg Mode     RegCTL[1]       RegCTL[0]               Note
+ * function:  This function writes data to RF register
+ * input:     net_device        *dev
+ *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
+ *            u32               offset   //target address to be written
+ *            u32               data    //the new register data to be written
+ * output:    none
+ * return:    none
+ * notice:    For RF8256 only.
* ===========================================================================
+ * Reg Mode    RegCTL[1]       RegCTL[0]               Note
  *             (Reg00[12])     (Reg00[10])
- *===========================================================
- *Reg_Mode0    0               x                       Reg 0 ~15(0x0 ~ 0xf)
- *------------------------------------------------------------------
- *Reg_Mode1    1               0                       Reg 16 ~30(0x1 ~ 0xf)
- *------------------------------------------------------------------
+ * ===========================================================================
+ * Reg_Mode0   0               x                       Reg 0 ~ 15(0x0 ~ 0xf)
+ * ---------------------------------------------------------------------------
+ * Reg_Mode1   1               0                       Reg 16 ~ 30(0x1 ~ 0xf)
+ * ---------------------------------------------------------------------------
  * Reg_Mode2   1               1                       Reg 31 ~ 45(0x1 ~ 0xf)
- *------------------------------------------------------------------
- * ****************************************************************************/
+ * ---------------------------------------------------------------------------
+ *****************************************************************************/
 void rtl8192_phy_RFSerialWrite(struct net_device *dev,
                               RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 {
@@ -240,17 +246,17 @@ void rtl8192_phy_RFSerialWrite(struct net_device *dev,
                new_offset = offset;
        }
 
-       // Put write addr in [5:0] and write data in [31:16]
+       /* Put write addr in [5:0] and write data in [31:16] */
        DataAndAddr = (data<<16) | (new_offset&0x3f);
 
-       // Write Operation
+       /* Write operation */
        rtl8192_setBBreg(dev, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 
 
        if (offset == 0x0)
                priv->RfReg0Value[eRFPath] = data;
 
-       // Switch back to Reg_Mode0;
+       /* Switch back to Reg_Mode0 */
        if (priv->rf_chip == RF_8256) {
                if (offset != 0) {
                        priv->RfReg0Value[eRFPath] &= 0xebf;
@@ -265,16 +271,16 @@ void rtl8192_phy_RFSerialWrite(struct net_device *dev,
 }
 
 /******************************************************************************
- *function:  This function set specific bits to RF register
- *   input:  net_device dev
- *          RF90_RADIO_PATH_E eRFPath //radio path of A/B/C/D
- *           u32       reg_addr //target addr to be modified
- *           u32       bitmask  //taget bit pos in the addr to be modified
- *           u32       data     //value to be write
- *  output:  none
- *  return:  none
- *  notice:
- * ****************************************************************************/
+ * function:  This function set specific bits to RF register
+ * input:     net_device        dev
+ *            RF90_RADIO_PATH_E eRFPath  //radio path of A/B/C/D
+ *            u32               reg_addr //target addr to be modified
+ *            u32               bitmask  //taget bit pos to be modified
+ *            u32               data     //value to be written
+ * output:    none
+ * return:    none
+ * notice:
+ *****************************************************************************/
 void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                          u32 reg_addr, u32 bitmask, u32 data)
 {
@@ -285,7 +291,8 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                return;
 
        if (priv->Rf_Mode == RF_OP_By_FW) {
-               if (bitmask != bMask12Bits) { // RF data is 12 bits only
+               if (bitmask != bMask12Bits) {
+                       /* RF data is 12 bits only */
                        reg = phy_FwRFSerialRead(dev, eRFPath, reg_addr);
                        bitshift =  rtl8192_CalculateBitShift(bitmask);
                        reg &= ~bitmask;
@@ -299,7 +306,8 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                udelay(200);
 
        } else {
-               if (bitmask != bMask12Bits) { // RF data is 12 bits only
+               if (bitmask != bMask12Bits) {
+                       /* RF data is 12 bits only */
                        reg = rtl8192_phy_RFSerialRead(dev, eRFPath, reg_addr);
                        bitshift =  rtl8192_CalculateBitShift(bitmask);
                        reg &= ~bitmask;
@@ -314,14 +322,14 @@ void rtl8192_phy_SetRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 }
 
 /******************************************************************************
- *function:  This function reads specific bits from RF register
- *   input:  net_device dev
- *           u32       reg_addr //target addr to be readback
- *           u32       bitmask  //taget bit pos in the addr to be readback
- *  output:  none
- *  return:  u32       data    //the readback register value
- *  notice:
- * ****************************************************************************/
+ * function:  This function reads specific bits from RF register
+ * input:     net_device        *dev
+ *            u32               reg_addr //target addr to be readback
+ *            u32               bitmask  //taget bit pos to be readback
+ * output:    none
+ * return:    u32               data     //the readback register value
+ * notice:
+ *****************************************************************************/
 u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                           u32 reg_addr, u32 bitmask)
 {
@@ -345,12 +353,14 @@ u32 rtl8192_phy_QueryRFReg(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
        }
 }
 /******************************************************************************
- *function:  We support firmware to execute RF-R/W.
- *   input:  dev
- *  output:  none
- *  return:  none
- *  notice:
- * ***************************************************************************/
+ * function:  We support firmware to execute RF-R/W.
+ * input:     net_device        *dev
+ *            RF90_RADIO_PATH_E eRFPath
+ *            u32               offset
+ * output:    none
+ * return:    u32
+ * notice:
+ ****************************************************************************/
 static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                              u32 offset)
 {
@@ -358,21 +368,23 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
        u32             data = 0;
        u8              time = 0;
        u32             tmp;
-       /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
-          not execute the scheme in the initial step. Otherwise, RF-R/W will waste
-          much time. This is only for site survey. */
-       // 1. Read operation need not insert data. bit 0-11
-       // 2. Write RF register address. Bit 12-19
+       /* Firmware RF Write control.
+        * We can not execute the scheme in the initial step.
+        * Otherwise, RF-R/W will waste much time.
+        * This is only for site survey. */
+       /* 1. Read operation need not insert data. bit 0-11 */
+       /* 2. Write RF register address. bit 12-19 */
        data |= ((offset&0xFF)<<12);
-       // 3. Write RF path.  bit 20-21
+       /* 3. Write RF path.  bit 20-21 */
        data |= ((eRFPath&0x3)<<20);
-       // 4. Set RF read indicator. bit 22=0
-       // 5. Trigger Fw to operate the command. bit 31
+       /* 4. Set RF read indicator. bit 22=0 */
+       /* 5. Trigger Fw to operate the command. bit 31 */
        data |= 0x80000000;
-       // 6. We can not execute read operation if bit 31 is 1.
+       /* 6. We can not execute read operation if bit 31 is 1. */
        read_nic_dword(dev, QPNR, &tmp);
        while (tmp & 0x80000000) {
-               // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
+               /* If FW can not finish RF-R/W for more than ?? times.
+                  We must reset FW. */
                if (time++ < 100) {
                        udelay(10);
                        read_nic_dword(dev, QPNR, &tmp);
@@ -380,12 +392,13 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
                        break;
                }
        }
-       // 7. Execute read operation.
+       /* 7. Execute read operation. */
        write_nic_dword(dev, QPNR, data);
-       // 8. Check if firmawre send back RF content.
+       /* 8. Check if firmware send back RF content. */
        read_nic_dword(dev, QPNR, &tmp);
        while (tmp & 0x80000000) {
-               // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
+               /* If FW can not finish RF-R/W for more than ?? times.
+                  We must reset FW. */
                if (time++ < 100) {
                        udelay(10);
                        read_nic_dword(dev, QPNR, &tmp);
@@ -397,39 +410,44 @@ static u32 phy_FwRFSerialRead(struct net_device *dev, RF90_RADIO_PATH_E eRFPath,
 
        return reg;
 
-}      /* phy_FwRFSerialRead */
+}
 
 /******************************************************************************
- *function:  We support firmware to execute RF-R/W.
- *   input:  dev
- *  output:  none
- *  return:  none
- *  notice:
- * ***************************************************************************/
+ * function:  We support firmware to execute RF-R/W.
+ * input:     net_device        *dev
+ *            RF90_RADIO_PATH_E eRFPath
+ *            u32               offset
+ *            u32               data
+ * output:    none
+ * return:    none
+ * notice:
+ ****************************************************************************/
 static void phy_FwRFSerialWrite(struct net_device *dev,
                                RF90_RADIO_PATH_E eRFPath, u32 offset, u32 data)
 {
        u8      time = 0;
        u32     tmp;
 
-       /* 2007/11/02 MH Firmware RF Write control. By Francis' suggestion, we can
-          not execute the scheme in the initial step. Otherwise, RF-R/W will waste
-          much time. This is only for site survey. */
+       /* Firmware RF Write control.
+        * We can not execute the scheme in the initial step.
+        * Otherwise, RF-R/W will waste much time.
+        * This is only for site survey. */
 
-       // 1. Set driver write bit and 12 bit data. bit 0-11
-       // 2. Write RF register address. bit 12-19
+       /* 1. Set driver write bit and 12 bit data. bit 0-11 */
+       /* 2. Write RF register address. bit 12-19 */
        data |= ((offset&0xFF)<<12);
-       // 3. Write RF path.  bit 20-21
+       /* 3. Write RF path.  bit 20-21 */
        data |= ((eRFPath&0x3)<<20);
-       // 4. Set RF write indicator. bit 22=1
+       /* 4. Set RF write indicator. bit 22=1 */
        data |= 0x400000;
-       // 5. Trigger Fw to operate the command. bit 31=1
+       /* 5. Trigger Fw to operate the command. bit 31=1 */
        data |= 0x80000000;
 
-       // 6. Write operation. We can not write if bit 31 is 1.
+       /* 6. Write operation. We can not write if bit 31 is 1. */
        read_nic_dword(dev, QPNR, &tmp);
        while (tmp & 0x80000000) {
-               // If FW can not finish RF-R/W for more than ?? times. We must reset FW.
+               /* If FW can not finish RF-R/W for more than ?? times.
+                  We must reset FW. */
                if (time++ < 100) {
                        udelay(10);
                        read_nic_dword(dev, QPNR, &tmp);
@@ -437,25 +455,25 @@ static void phy_FwRFSerialWrite(struct net_device *dev,
                        break;
                }
        }
-       // 7. No matter check bit. We always force the write. Because FW will
-       //    not accept the command.
+       /* 7. No matter check bit. We always force the write.
+          Because FW will not accept the command. */
        write_nic_dword(dev, QPNR, data);
-       /* 2007/11/02 MH Acoording to test, we must delay 20us to wait firmware
+       /* According to test, we must delay 20us to wait firmware
           to finish RF write operation. */
-       /* 2008/01/17 MH We support delay in firmware side now. */
+       /* We support delay in firmware side now. */
 
-}      /* phy_FwRFSerialWrite */
+}
 
 
 /******************************************************************************
- *function:  This function read BB parameters from Header file we gen,
- *          and do register read/write
- *   input:  dev
- *  output:  none
- *  return:  none
- *  notice:  BB parameters may change all the time, so please make
- *           sure it has been synced with the newest.
- * ***************************************************************************/
+ * function:  This function reads BB parameters from header file we generate,
+ *            and do register read/write
+ * input:     net_device       *dev
+ * output:    none
+ * return:    none
+ * notice:    BB parameters may change all the time, so please make
+ *            sure it has been synced with the newest.
+ *****************************************************************************/
 void rtl8192_phy_configmac(struct net_device *dev)
 {
        u32 dwArrayLen = 0, i;
@@ -486,13 +504,14 @@ void rtl8192_phy_configmac(struct net_device *dev)
 }
 
 /******************************************************************************
- *function:  This function does dirty work
- *   input:  dev
- *  output:  none
- *  return:  none
- *  notice:  BB parameters may change all the time, so please make
- *           sure it has been synced with the newest.
- * ***************************************************************************/
+ * function:  This function does dirty work
+ * input:     net_device       *dev
+ *            u8                ConfigType
+ * output:    none
+ * return:    none
+ * notice:    BB parameters may change all the time, so please make
+ *            sure it has been synced with the newest.
+ *****************************************************************************/
 
 void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 {
@@ -523,113 +542,134 @@ void rtl8192_phyConfigBB(struct net_device *dev, u8 ConfigType)
 
 }
 /******************************************************************************
- *function:  This function initialize Register definition offset for Radio Path
- *          A/B/C/D
- *   input:  net_device dev
- *  output:  none
- *  return:  none
- *  notice:  Initialization value here is constant and it should never be changed
- * ***************************************************************************/
+ * function:  This function initializes Register definition offset for
+ *            Radio Path A/B/C/D
+ * input:     net_device       *dev
+ * output:    none
+ * return:    none
+ * notice:    Initialization value here is constant and it should never
+ *            be changed
+ *****************************************************************************/
 void rtl8192_InitBBRFRegDef(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
-// RF Interface Software Control
-       priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
-       priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
-       priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
-       priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
-
-       // RF Interface Readback Value
-       priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
-       priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
-       priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
-       priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
-
-       // RF Interface Output (and Enable)
-       priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
-       priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
-       priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x868
-       priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;// 16 LSBs if read 32-bit from 0x86C
-
-       // RF Interface (Output and)  Enable
-       priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
-       priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
-       priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A)
-       priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;// 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E)
-
-       //Addr of LSSI. Write RF register by driver
-       priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
+       /* RF Interface Software Control */
+       /* 16 LSBs if read 32-bit from 0x870 */
+       priv->PHYRegDef[RF90_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW;
+       /* 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872) */
+       priv->PHYRegDef[RF90_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW;
+       /* 16 LSBs if read 32-bit from 0x874 */
+       priv->PHYRegDef[RF90_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;
+       /* 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876) */
+       priv->PHYRegDef[RF90_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;
+
+       /* RF Interface Readback Value */
+       /* 16 LSBs if read 32-bit from 0x8E0 */
+       priv->PHYRegDef[RF90_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB;
+       /* 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2) */
+       priv->PHYRegDef[RF90_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;
+       /* 16 LSBs if read 32-bit from 0x8E4 */
+       priv->PHYRegDef[RF90_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;
+       /* 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6) */
+       priv->PHYRegDef[RF90_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;
+
+       /* RF Interface Output (and Enable) */
+       /* 16 LSBs if read 32-bit from 0x860 */
+       priv->PHYRegDef[RF90_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE;
+       /* 16 LSBs if read 32-bit from 0x864 */
+       priv->PHYRegDef[RF90_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE;
+       /* 16 LSBs if read 32-bit from 0x868 */
+       priv->PHYRegDef[RF90_PATH_C].rfintfo = rFPGA0_XC_RFInterfaceOE;
+       /* 16 LSBs if read 32-bit from 0x86C */
+       priv->PHYRegDef[RF90_PATH_D].rfintfo = rFPGA0_XD_RFInterfaceOE;
+
+       /* RF Interface (Output and) Enable */
+       /* 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862) */
+       priv->PHYRegDef[RF90_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE;
+       /* 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866) */
+       priv->PHYRegDef[RF90_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE;
+       /* 16 MSBs if read 32-bit from 0x86A (16-bit for 0x86A) */
+       priv->PHYRegDef[RF90_PATH_C].rfintfe = rFPGA0_XC_RFInterfaceOE;
+       /* 16 MSBs if read 32-bit from 0x86C (16-bit for 0x86E) */
+       priv->PHYRegDef[RF90_PATH_D].rfintfe = rFPGA0_XD_RFInterfaceOE;
+
+       /* Addr of LSSI. Write RF register by driver */
+       priv->PHYRegDef[RF90_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter;
        priv->PHYRegDef[RF90_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
        priv->PHYRegDef[RF90_PATH_C].rf3wireOffset = rFPGA0_XC_LSSIParameter;
        priv->PHYRegDef[RF90_PATH_D].rf3wireOffset = rFPGA0_XD_LSSIParameter;
 
-       // RF parameter
-       priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
+       /* RF parameter */
+       /* BB Band Select */
+       priv->PHYRegDef[RF90_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;
        priv->PHYRegDef[RF90_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
        priv->PHYRegDef[RF90_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
        priv->PHYRegDef[RF90_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 
-       // Tx AGC Gain Stage (same for all path. Should we remove this?)
-       priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
-       priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
-       priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
-       priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
-
-       // Tranceiver A~D HSSI Parameter-1
-       priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
-       priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
-       priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;  //wire control parameter1
-       priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;  //wire control parameter1
-
-       // Tranceiver A~D HSSI Parameter-2
-       priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
-       priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
-       priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;  //wire control parameter2
-       priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;  //wire control parameter1
-
-       // RF switch Control
-       priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
+       /* Tx AGC Gain Stage (same for all path. Should we remove this?) */
+       priv->PHYRegDef[RF90_PATH_A].rfTxGainStage = rFPGA0_TxGainStage;
+       priv->PHYRegDef[RF90_PATH_B].rfTxGainStage = rFPGA0_TxGainStage;
+       priv->PHYRegDef[RF90_PATH_C].rfTxGainStage = rFPGA0_TxGainStage;
+       priv->PHYRegDef[RF90_PATH_D].rfTxGainStage = rFPGA0_TxGainStage;
+
+       /* Tranceiver A~D HSSI Parameter-1 */
+       /* wire control parameter1 */
+       priv->PHYRegDef[RF90_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;
+       priv->PHYRegDef[RF90_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;
+       priv->PHYRegDef[RF90_PATH_C].rfHSSIPara1 = rFPGA0_XC_HSSIParameter1;
+       priv->PHYRegDef[RF90_PATH_D].rfHSSIPara1 = rFPGA0_XD_HSSIParameter1;
+
+       /* Tranceiver A~D HSSI Parameter-2 */
+       /* wire control parameter2 */
+       priv->PHYRegDef[RF90_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;
+       priv->PHYRegDef[RF90_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;
+       priv->PHYRegDef[RF90_PATH_C].rfHSSIPara2 = rFPGA0_XC_HSSIParameter2;
+       priv->PHYRegDef[RF90_PATH_D].rfHSSIPara2 = rFPGA0_XD_HSSIParameter2;
+
+       /* RF Switch Control */
+       /* TR/Ant switch control */
+       priv->PHYRegDef[RF90_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl;
        priv->PHYRegDef[RF90_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
        priv->PHYRegDef[RF90_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
        priv->PHYRegDef[RF90_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 
-       // AGC control 1
+       /* AGC control 1 */
        priv->PHYRegDef[RF90_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
        priv->PHYRegDef[RF90_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
        priv->PHYRegDef[RF90_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
        priv->PHYRegDef[RF90_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 
-       // AGC control 2
+       /* AGC control 2 */
        priv->PHYRegDef[RF90_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
        priv->PHYRegDef[RF90_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
        priv->PHYRegDef[RF90_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
        priv->PHYRegDef[RF90_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 
-       // RX AFE control 1
+       /* RX AFE control 1 */
        priv->PHYRegDef[RF90_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
        priv->PHYRegDef[RF90_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
        priv->PHYRegDef[RF90_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
        priv->PHYRegDef[RF90_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 
-       // RX AFE control 1
+       /* RX AFE control 1 */
        priv->PHYRegDef[RF90_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
        priv->PHYRegDef[RF90_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
        priv->PHYRegDef[RF90_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
        priv->PHYRegDef[RF90_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 
-       // Tx AFE control 1
+       /* Tx AFE control 1 */
        priv->PHYRegDef[RF90_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
        priv->PHYRegDef[RF90_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
        priv->PHYRegDef[RF90_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
        priv->PHYRegDef[RF90_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 
-       // Tx AFE control 2
+       /* Tx AFE control 2 */
        priv->PHYRegDef[RF90_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
        priv->PHYRegDef[RF90_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
        priv->PHYRegDef[RF90_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
        priv->PHYRegDef[RF90_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 
-       // Tranceiver LSSI Readback
+       /* Tranceiver LSSI Readback */
        priv->PHYRegDef[RF90_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
        priv->PHYRegDef[RF90_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
        priv->PHYRegDef[RF90_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
@@ -637,14 +677,16 @@ void rtl8192_InitBBRFRegDef(struct net_device *dev)
 
 }
 /******************************************************************************
- *function:  This function is to write register and then readback to make sure whether BB and RF is OK
- *   input:  net_device dev
- *          HW90_BLOCK_E CheckBlock
- *          RF90_RADIO_PATH_E eRFPath  //only used when checkblock is HW90_BLOCK_RF
- *  output:  none
- *  return:  return whether BB and RF is ok(0:OK; 1:Fail)
- *  notice:  This function may be removed in the ASIC
- * ***************************************************************************/
+ * function:  This function is to write register and then readback to make
+ *            sure whether BB and RF is OK
+ * input:     net_device        *dev
+ *            HW90_BLOCK_E      CheckBlock
+ *            RF90_RADIO_PATH_E eRFPath  //only used when checkblock is
+ *                                       //HW90_BLOCK_RF
+ * output:    none
+ * return:    return whether BB and RF is ok (0:OK, 1:Fail)
+ * notice:    This function may be removed in the ASIC
+ ******************************************************************************/
 u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
                            RF90_RADIO_PATH_E eRFPath)
 {
@@ -652,7 +694,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
        u32 i, CheckTimes = 4, dwRegRead = 0;
        u32 WriteAddr[4];
        u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
-       // Initialize register address offset to be checked
+       /* Initialize register address offset to be checked */
        WriteAddr[HW90_BLOCK_MAC] = 0x100;
        WriteAddr[HW90_BLOCK_PHY0] = 0x900;
        WriteAddr[HW90_BLOCK_PHY1] = 0x800;
@@ -660,9 +702,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
        RT_TRACE(COMP_PHY, "=======>%s(), CheckBlock:%d\n", __FUNCTION__, CheckBlock);
        for (i = 0; i < CheckTimes; i++) {
 
-               //
-               // Write Data to register and readback
-               //
+               /* Write data to register and readback */
                switch (CheckBlock) {
                case HW90_BLOCK_MAC:
                        RT_TRACE(COMP_ERR, "PHY_CheckBBRFOK(): Never Write 0x100 here!");
@@ -677,7 +717,8 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
                case HW90_BLOCK_RF:
                        WriteData[i] &= 0xfff;
                        rtl8192_phy_SetRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits, WriteData[i]);
-                       // TODO: we should not delay for such a long time. Ask SD3
+                       /* TODO: we should not delay for such a long time.
+                          Ask SD3 */
                        msleep(1);
                        dwRegRead = rtl8192_phy_QueryRFReg(dev, eRFPath, WriteAddr[HW90_BLOCK_RF], bMask12Bits);
                        msleep(1);
@@ -689,9 +730,7 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
                }
 
 
-               //
-               // Check whether readback data is correct
-               //
+               /* Check whether readback data is correct */
                if (dwRegRead != WriteData[i]) {
                        RT_TRACE((COMP_PHY|COMP_ERR), "====>error=====dwRegRead: %x, WriteData: %x \n", dwRegRead, WriteData[i]);
                        ret = 1;
@@ -704,93 +743,95 @@ u8 rtl8192_phy_checkBBAndRF(struct net_device *dev, HW90_BLOCK_E CheckBlock,
 
 
 /******************************************************************************
- *function:  This function initialize BB&RF
- *   input:  net_device dev
- *  output:  none
- *  return:  none
- *  notice:  Initialization value may change all the time, so please make
- *           sure it has been synced with the newest.
- * ***************************************************************************/
+ * function:  This function initializes BB&RF
+ * input:     net_device       *dev
+ * output:    none
+ * return:    none
+ * notice:    Initialization value may change all the time, so please make
+ *            sure it has been synced with the newest.
+ ******************************************************************************/
 void rtl8192_BB_Config_ParaFile(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
        u8 reg_u8 = 0, eCheckItem = 0, rtStatus = 0;
        u32 reg_u32 = 0;
        /**************************************
-       //<1>Initialize BaseBand
-       **************************************/
+        * <1> Initialize BaseBand
+        *************************************/
 
-       /*--set BB Global Reset--*/
+       /* --set BB Global Reset-- */
        read_nic_byte(dev, BB_GLOBAL_RESET, &reg_u8);
        write_nic_byte(dev, BB_GLOBAL_RESET, (reg_u8|BB_GLOBAL_RESET_BIT));
        mdelay(50);
-       /*---set BB reset Active---*/
+       /* ---set BB reset Active--- */
        read_nic_dword(dev, CPU_GEN, &reg_u32);
        write_nic_dword(dev, CPU_GEN, (reg_u32&(~CPU_GEN_BB_RST)));
 
-       /*----Ckeck FPGAPHY0 and PHY1 board is OK----*/
-       // TODO: this function should be removed on ASIC , Emily 2007.2.2
+       /* ----Ckeck FPGAPHY0 and PHY1 board is OK---- */
+       /* TODO: this function should be removed on ASIC */
        for (eCheckItem = (HW90_BLOCK_E)HW90_BLOCK_PHY0; eCheckItem <= HW90_BLOCK_PHY1; eCheckItem++) {
-               rtStatus  = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); //don't care RF path
+               rtStatus  = rtl8192_phy_checkBBAndRF(dev, (HW90_BLOCK_E)eCheckItem, (RF90_RADIO_PATH_E)0); /* don't care RF path */
                if (rtStatus != 0) {
                        RT_TRACE((COMP_ERR | COMP_PHY), "PHY_RF8256_Config():Check PHY%d Fail!!\n", eCheckItem-1);
                        return;
                }
        }
-       /*---- Set CCK and OFDM Block "OFF"----*/
+       /* ---- Set CCK and OFDM Block "OFF"---- */
        rtl8192_setBBreg(dev, rFPGA0_RFMOD, bCCKEn|bOFDMEn, 0x0);
-       /*----BB Register Initilazation----*/
-       //==m==>Set PHY REG From Header<==m==
+       /* ----BB Register Initilazation---- */
+       /* ==m==>Set PHY REG From Header<==m== */
        rtl8192_phyConfigBB(dev, BaseBand_Config_PHY_REG);
 
-       /*----Set BB reset de-Active----*/
+       /* ----Set BB reset de-Active---- */
        read_nic_dword(dev, CPU_GEN, &reg_u32);
        write_nic_dword(dev, CPU_GEN, (reg_u32|CPU_GEN_BB_RST));
 
-       /*----BB AGC table Initialization----*/
-       //==m==>Set PHY REG From Header<==m==
+       /* ----BB AGC table Initialization---- */
+       /* ==m==>Set PHY REG From Header<==m== */
        rtl8192_phyConfigBB(dev, BaseBand_Config_AGC_TAB);
 
-       /*----Enable XSTAL ----*/
+       /* ----Enable XSTAL ---- */
        write_nic_byte_E(dev, 0x5e, 0x00);
        if (priv->card_8192_version == (u8)VERSION_819xU_A) {
-               //Antenna gain offset from B/C/D to A
+               /* Antenna gain offset from B/C/D to A */
                reg_u32 = (priv->AntennaTxPwDiff[1]<<4 | priv->AntennaTxPwDiff[0]);
                rtl8192_setBBreg(dev, rFPGA0_TxGainStage, (bXBTxAGC|bXCTxAGC), reg_u32);
 
-               //XSTALLCap
+               /* XSTALLCap */
                reg_u32 = priv->CrystalCap & 0xf;
                rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, bXtalCap, reg_u32);
        }
 
-       // Check if the CCK HighPower is turned ON.
-       // This is used to calculate PWDB.
+       /* Check if the CCK HighPower is turned ON.
+          This is used to calculate PWDB. */
        priv->bCckHighPower = (u8)(rtl8192_QueryBBReg(dev, rFPGA0_XA_HSSIParameter2, 0x200));
        return;
 }
 /******************************************************************************
- *function:  This function initialize BB&RF
- *   input:  net_device dev
- *  output:  none
- *  return:  none
- *  notice:  Initialization value may change all the time, so please make
- *           sure it has been synced with the newest.
- * ***************************************************************************/
+ * function:  This function initializes BB&RF
+ * input:     net_device       *dev
+ * output:    none
+ * return:    none
+ * notice:    Initialization value may change all the time, so please make
+ *            sure it has been synced with the newest.
+ *****************************************************************************/
 void rtl8192_BBConfig(struct net_device *dev)
 {
        rtl8192_InitBBRFRegDef(dev);
-       //config BB&RF. As hardCode based initialization has not been well
-       //implemented, so use file first.FIXME:should implement it for hardcode?
+       /* config BB&RF. As hardCode based initialization has not been well
+        * implemented, so use file first.
+        * FIXME: should implement it for hardcode? */
        rtl8192_BB_Config_ParaFile(dev);
        return;
 }
 
 /******************************************************************************
- *function:  This function obtains the initialization value of Tx power Level offset
- *   input:  net_device dev
- *  output:  none
- *  return:  none
- * ***************************************************************************/
+ * function:  This function obtains the initialization value of Tx power Level
+ *            offset
+ * input:     net_device       *dev
+ * output:    none
+ * return:    none
+ *****************************************************************************/
 void rtl8192_phy_getTxPower(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -802,7 +843,7 @@ void rtl8192_phy_getTxPower(struct net_device *dev)
        read_nic_dword(dev, rTxAGC_Mcs11_Mcs08, &priv->MCSTxPowerLevelOriginalOffset[4]);
        read_nic_dword(dev, rTxAGC_Mcs15_Mcs12, &priv->MCSTxPowerLevelOriginalOffset[5]);
 
-       // read rx initial gain
+       /* Read rx initial gain */
        read_nic_byte(dev, rOFDM0_XAAGCCore1, &priv->DefaultInitialGain[0]);
        read_nic_byte(dev, rOFDM0_XBAGCCore1, &priv->DefaultInitialGain[1]);
        read_nic_byte(dev, rOFDM0_XCAGCCore1, &priv->DefaultInitialGain[2]);
@@ -811,25 +852,27 @@ void rtl8192_phy_getTxPower(struct net_device *dev)
                priv->DefaultInitialGain[0], priv->DefaultInitialGain[1],
                priv->DefaultInitialGain[2], priv->DefaultInitialGain[3]);
 
-       // read framesync
+       /* Read framesync */
        read_nic_byte(dev, rOFDM0_RxDetector3, &priv->framesync);
        read_nic_byte(dev, rOFDM0_RxDetector2, &tmp);
        priv->framesyncC34 = tmp;
        RT_TRACE(COMP_INIT, "Default framesync (0x%x) = 0x%x \n",
                rOFDM0_RxDetector3, priv->framesync);
 
-       // read SIFS (save the value read fome MACPHY_REG.txt)
+       /* Read SIFS (save the value read fome MACPHY_REG.txt) */
        read_nic_word(dev, SIFS, &priv->SifsTime);
 
        return;
 }
 
 /******************************************************************************
- *function:  This function obtains the initialization value of Tx power Level offset
- *   input:  net_device dev
- *  output:  none
- *  return:  none
- * ***************************************************************************/
+ * function:  This function sets the initialization value of Tx power Level
+ *            offset
+ * input:     net_device        *dev
+ *            u8                channel
+ * output:    none
+ * return:    none
+ ******************************************************************************/
 void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -849,11 +892,11 @@ void rtl8192_phy_setTxPower(struct net_device *dev, u8 channel)
 }
 
 /******************************************************************************
- *function:  This function check Rf chip to do RF config
- *   input:  net_device dev
- *  output:  none
- *  return:  only 8256 is supported
- * ***************************************************************************/
+ * function:  This function checks Rf chip to do RF config
+ * input:     net_device       *dev
+ * output:    none
+ * return:    only 8256 is supported
+ ******************************************************************************/
 void rtl8192_phy_RFConfig(struct net_device *dev)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -870,23 +913,25 @@ void rtl8192_phy_RFConfig(struct net_device *dev)
 }
 
 /******************************************************************************
- *function:  This function update Initial gain
- *   input:  net_device dev
- *  output:  none
- *  return:  As Windows has not implemented this, wait for complement
- * ***************************************************************************/
+ * function:  This function updates Initial gain
+ * input:     net_device       *dev
+ * output:    none
+ * return:    As Windows has not implemented this, wait for complement
+ ******************************************************************************/
 void rtl8192_phy_updateInitGain(struct net_device *dev)
 {
        return;
 }
 
 /******************************************************************************
- *function:  This function read RF parameters from general head file, and do RF 3-wire
- *   input:  net_device dev
- *  output:  none
- *  return:  return code show if RF configuration is successful(0:pass, 1:fail)
- *    Note:  Delay may be required for RF configuration
- * ***************************************************************************/
+ * function:  This function read RF parameters from general head file,
+ *            and do RF 3-wire
+ * input:     net_device       *dev
+ *            RF90_RADIO_PATH_E eRFPath
+ * output:    none
+ * return:    return code show if RF configuration is successful(0:pass, 1:fail)
+ * notice:    Delay may be required for RF configuration
+ *****************************************************************************/
 u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
                                      RF90_RADIO_PATH_E eRFPath)
 {
@@ -951,13 +996,13 @@ u8 rtl8192_phy_ConfigRFWithHeaderFile(struct net_device *dev,
 
 }
 /******************************************************************************
- *function:  This function set Tx Power of the channel
- *   input:  struct net_device *dev
- *          u8                 channel
- *  output:  none
- *  return:  none
- *    Note:
- * ***************************************************************************/
+ * function:  This function sets Tx Power of the channel
+ * input:     net_device        *dev
+ *            u8                channel
+ * output:    none
+ * return:    none
+ * notice:
+ ******************************************************************************/
 void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -987,13 +1032,13 @@ void rtl8192_SetTxPowerLevel(struct net_device *dev, u8 channel)
 }
 
 /******************************************************************************
- *function:  This function set RF state on or off
- *   input:  struct net_device *dev
- *          RT_RF_POWER_STATE eRFPowerState  //Power State to set
- *  output:  none
- *  return:  none
- *    Note:
- * ***************************************************************************/
+ * function:  This function sets RF state on or off
+ * input:     net_device         *dev
+ *            RT_RF_POWER_STATE  eRFPowerState  //Power State to set
+ * output:    none
+ * return:    none
+ * notice:
+ *****************************************************************************/
 bool rtl8192_SetRFPowerState(struct net_device *dev,
                             RT_RF_POWER_STATE eRFPowerState)
 {
@@ -1012,19 +1057,19 @@ bool rtl8192_SetRFPowerState(struct net_device *dev,
                case RF_8256:
                switch (eRFPowerState) {
                        case eRfOn:
-       //RF-A, RF-B
-                                       //enable RF-Chip A/B
-                                       rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1);      // 0x860[4]
-                                       //analog to digital on
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3);// 0x88c[9:8]
-                                       //digital to analog on
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); // 0x880[4:3]
-                                       //rx antenna on
-                                       rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3);// 0xc04[1:0]
-                                       //rx antenna on
-                                       rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3);// 0xd04[1:0]
-                                       //analog to digital part2 on
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); // 0x880[6:5]
+                               /* RF-A, RF-B */
+                               /* enable RF-Chip A/B */
+                               rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x1); /* 0x860[4] */
+                               /* analog to digital on */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0x300, 0x3); /* 0x88c[9:8] */
+                               /* digital to analog on */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x3); /* 0x880[4:3] */
+                               /* rx antenna on */
+                               rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0x3, 0x3); /* 0xc04[1:0] */
+                               /* rx antenna on */
+                               rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0x3, 0x3); /* 0xd04[1:0] */
+                               /* analog to digital part2 on */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x3); /* 0x880[6:5] */
 
                                break;
 
@@ -1033,19 +1078,19 @@ bool rtl8192_SetRFPowerState(struct net_device *dev,
                                break;
 
                        case eRfOff:
-                                       //RF-A, RF-B
-                                       //disable RF-Chip A/B
-                                       rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0);      // 0x860[4]
-                                       //analog to digital off, for power save
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0);// 0x88c[11:8]
-                                       //digital to analog off, for power save
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); // 0x880[4:3]
-                                       //rx antenna off
-                                       rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0);// 0xc04[3:0]
-                                       //rx antenna off
-                                       rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0);// 0xd04[3:0]
-                                       //analog to digital part2 off, for power save
-                                       rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); // 0x880[6:5]
+                               /* RF-A, RF-B */
+                               /* disable RF-Chip A/B */
+                               rtl8192_setBBreg(dev, rFPGA0_XA_RFInterfaceOE, BIT4, 0x0); /* 0x860[4] */
+                               /* analog to digital off, for power save */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter4, 0xf00, 0x0); /* 0x88c[11:8] */
+                               /* digital to analog off, for power save */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x18, 0x0); /* 0x880[4:3] */
+                               /* rx antenna off */
+                               rtl8192_setBBreg(dev, rOFDM0_TRxPathEnable, 0xf, 0x0); /* 0xc04[3:0] */
+                               /* rx antenna off */
+                               rtl8192_setBBreg(dev, rOFDM1_TRxPathEnable, 0xf, 0x0); /* 0xd04[3:0] */
+                               /* analog to digital part2 off, for power save */
+                               rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x60, 0x0); /* 0x880[6:5] */
 
                                break;
 
@@ -1061,36 +1106,32 @@ bool rtl8192_SetRFPowerState(struct net_device *dev,
        }
 #ifdef TO_DO_LIST
        if (bResult) {
-               // Update current RF state variable.
+               /* Update current RF state variable. */
                pHalData->eRFPowerState = eRFPowerState;
                switch (pHalData->RFChipID) {
                        case RF_8256:
                switch (pHalData->eRFPowerState) {
                                case eRfOff:
-                                       //
-                                       //If Rf off reason is from IPS, Led should blink with no link, by Maddest 071015
-                                       //
+                                       /* If Rf off reason is from IPS, LED should blink with no link */
                                        if (pMgntInfo->RfOffReason == RF_CHANGE_BY_IPS)
                                                Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
                                        else
-                                               // Turn off LED if RF is not ON.
+                                               /* Turn off LED if RF is not ON. */
                                                Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_POWER_OFF);
                                        break;
 
                                case eRfOn:
-                                       // Turn on RF we are still linked, which might happen when
-                                       // we quickly turn off and on HW RF. 2006.05.12, by rcnjko.
+                                       /* Turn on RF we are still linked, which might happen when we quickly turn off and on HW RF. */
                                        if (pMgntInfo->bMediaConnect == TRUE)
                                                Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_LINK);
                                        else
-                                               // Turn off LED if RF is not ON.
+                                               /* Turn off LED if RF is not ON. */
                                                Adapter->HalFunc.LedControlHandler(Adapter, LED_CTL_NO_LINK);
                                        break;
 
                                default:
-                                       // do nothing.
                                        break;
-                               }// Switch RF state
+                               }
                                break;
 
                                default:
@@ -1105,19 +1146,19 @@ bool rtl8192_SetRFPowerState(struct net_device *dev,
        return bResult;
 }
 
-/****************************************************************************************
- *function:  This function set command table variable(struct SwChnlCmd).
- *   input:  SwChnlCmd*                CmdTable        //table to be set.
- *          u32                CmdTableIdx     //variable index in table to be set
- *          u32                CmdTableSz      //table size.
- *          SwChnlCmdID        CmdID           //command ID to set.
- *          u32                Para1
- *          u32                Para2
- *          u32                msDelay
- *  output:
- *  return:  true if finished, false otherwise
- *    Note:
- * ************************************************************************************/
+/******************************************************************************
+ * function:  This function sets command table variable (struct SwChnlCmd).
+ * input:     SwChnlCmd      *CmdTable    //table to be set
+ *            u32            CmdTableIdx  //variable index in table to be set
+ *            u32            CmdTableSz   //table size
+ *            SwChnlCmdID    CmdID        //command ID to set
+ *            u32            Para1
+ *            u32            Para2
+ *            u32            msDelay
+ * output:
+ * return:    true if finished, false otherwise
+ * notice:
+ ******************************************************************************/
 u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
                                 u32 CmdTableSz, SwChnlCmdID CmdID, u32 Para1,
                                 u32 Para2, u32 msDelay)
@@ -1143,16 +1184,17 @@ u8 rtl8192_phy_SetSwChnlCmdArray(SwChnlCmd *CmdTable, u32 CmdTableIdx,
        return true;
 }
 /******************************************************************************
- *function:  This function set channel step by step
- *   input:  struct net_device *dev
- *          u8                 channel
- *          u8*                stage //3 stages
- *          u8*                step  //
- *          u32*               delay //whether need to delay
- *  output:  store new stage, step and delay for next step(combine with function above)
- *  return:  true if finished, false otherwise
- *    Note:  Wait for simpler function to replace it //wb
- * ***************************************************************************/
+ * function:  This function sets channel step by step
+ * input:     net_device        *dev
+ *            u8                channel
+ *            u8                *stage   //3 stages
+ *            u8                *step
+ *            u32               *delay   //whether need to delay
+ * output:    store new stage, step and delay for next step
+ *            (combine with function above)
+ * return:    true if finished, false otherwise
+ * notice:    Wait for simpler function to replace it
+ *****************************************************************************/
 u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
                                u8 *step, u32 *delay)
 {
@@ -1169,25 +1211,27 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
        RT_TRACE(COMP_CH, "====>%s()====stage:%d, step:%d, channel:%d\n", __FUNCTION__, *stage, *step, channel);
        if (!IsLegalChannel(priv->ieee80211, channel)) {
                RT_TRACE(COMP_ERR, "=============>set to illegal channel:%d\n", channel);
-               return true; //return true to tell upper caller function this channel setting is finished! Or it will in while loop.
+               /* return true to tell upper caller function this channel
+                  setting is finished! Or it will in while loop. */
+               return true;
        }
-//FIXME:need to check whether channel is legal or not here.WB
+/* FIXME: need to check whether channel is legal or not here */
 
 
-               // <1> Fill up pre common command.
+               /* <1> Fill up pre common command. */
                PreCommonCmdCnt = 0;
                rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
                                        CmdID_SetTxPowerLevel, 0, 0, 0);
                rtl8192_phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
                                        CmdID_End, 0, 0, 0);
 
-               // <2> Fill up post common command.
+               /* <2> Fill up post common command. */
                PostCommonCmdCnt = 0;
 
                rtl8192_phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
                                        CmdID_End, 0, 0, 0);
 
-               // <3> Fill up RF dependent command.
+               /* <3> Fill up RF dependent command. */
                RfDependCmdCnt = 0;
                switch (priv->rf_chip) {
                case RF_8225:
@@ -1202,7 +1246,7 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
                        break;
 
                case RF_8256:
-                       // TEST!! This is not the table for 8256!!
+                       /* TEST!! This is not the table for 8256!! */
                        if (!(channel >= 1 && channel <= 14)) {
                                RT_TRACE(COMP_ERR, "illegal channel for Zebra 8256: %d\n", channel);
                                return true;
@@ -1249,7 +1293,8 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
 
                        switch (CurrentCmd->CmdID) {
                        case CmdID_SetTxPowerLevel:
-                               if (priv->card_8192_version == (u8)VERSION_819xU_A) //xiong: consider it later!
+                               if (priv->card_8192_version == (u8)VERSION_819xU_A)
+                                       /* consider it later! */
                                        rtl8192_SetTxPowerLevel(dev, channel);
                                break;
                        case CmdID_WritePortUlong:
@@ -1279,13 +1324,13 @@ u8 rtl8192_phy_SwChnlStepByStep(struct net_device *dev, u8 channel, u8 *stage,
 }
 
 /******************************************************************************
- *function:  This function does actually set channel work
- *   input:  struct net_device *dev
- *          u8                 channel
- *  output:  none
- *  return:  noin
- *    Note:  We should not call this function directly
- * ***************************************************************************/
+ * function:  This function does actually set channel work
+ * input:     net_device        *dev
+ *            u8                channel
+ * output:    none
+ * return:    none
+ * notice:    We should not call this function directly
+ *****************************************************************************/
 void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -1297,12 +1342,12 @@ void rtl8192_phy_FinishSwChnlNow(struct net_device *dev, u8 channel)
        }
 }
 /******************************************************************************
- *function:  Callback routine of the work item for switch channel.
- *   input:
+ * function:  Callback routine of the work item for switch channel.
+ * input:     net_device       *dev
  *
- *  output:  none
- *  return:  noin
- * ***************************************************************************/
+ * output:    none
+ * return:    none
+ *****************************************************************************/
 void rtl8192_SwChnl_WorkItem(struct net_device *dev)
 {
 
@@ -1317,13 +1362,13 @@ void rtl8192_SwChnl_WorkItem(struct net_device *dev)
 }
 
 /******************************************************************************
- *function:  This function scheduled actual work item to set channel
- *   input:  net_device dev
- *          u8         channel //channel to set
- *  output:  none
- *  return:  return code show if workitem is scheduled(1:pass, 0:fail)
- *    Note:  Delay may be required for RF configuration
- * ***************************************************************************/
+ * function:  This function scheduled actual work item to set channel
+ * input:     net_device        *dev
+ *            u8                channel   //channel to set
+ * output:    none
+ * return:    return code show if workitem is scheduled (1:pass, 0:fail)
+ * notice:    Delay may be required for RF configuration
+ ******************************************************************************/
 u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
 {
        struct r8192_priv *priv = ieee80211_priv(dev);
@@ -1333,7 +1378,7 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
        if (priv->SwChnlInProgress)
                return false;
 
-       //--------------------------------------------
+       /* -------------------------------------------- */
        switch (priv->ieee80211->mode) {
        case WIRELESS_MODE_A:
        case WIRELESS_MODE_N_5G:
@@ -1356,7 +1401,7 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
                }
                break;
        }
-       //--------------------------------------------
+       /* -------------------------------------------- */
 
        priv->SwChnlInProgress = true;
        if (channel == 0)
@@ -1374,17 +1419,14 @@ u8 rtl8192_phy_SwChnl(struct net_device *dev, u8 channel)
 }
 
 
-//
 /******************************************************************************
- *function:  Callback routine of the work item for set bandwidth mode.
- *   input:  struct net_device *dev
- *          HT_CHANNEL_WIDTH   Bandwidth  //20M or 40M
- *          HT_EXTCHNL_OFFSET Offset      //Upper, Lower, or Don't care
- *  output:  none
- *  return:  none
- *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
- *          test whether current work in the queue or not.//do I?
- * ***************************************************************************/
+ * function:  Callback routine of the work item for set bandwidth mode.
+ * input:     net_device        *dev
+ * output:    none
+ * return:    none
+ * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
+ *            test whether current work in the queue or not.//do I?
+ *****************************************************************************/
 void rtl8192_SetBWModeWorkItem(struct net_device *dev)
 {
 
@@ -1400,19 +1442,19 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
                return;
        }
 
-       //<1>Set MAC register
+       /* <1> Set MAC register */
        read_nic_byte(dev, BW_OPMODE, &regBwOpMode);
 
        switch (priv->CurrentChannelBW) {
                case HT_CHANNEL_WIDTH_20:
                        regBwOpMode |= BW_OPMODE_20MHZ;
-                      // 2007/02/07 Mark by Emily because we have not verify whether this register works
+                       /* We have not verify whether this register works */
                        write_nic_byte(dev, BW_OPMODE, regBwOpMode);
                        break;
 
                case HT_CHANNEL_WIDTH_20_40:
                        regBwOpMode &= ~BW_OPMODE_20MHZ;
-                       // 2007/02/07 Mark by Emily because we have not verify whether this register works
+                       /* We have not verify whether this register works */
                        write_nic_byte(dev, BW_OPMODE, regBwOpMode);
                        break;
 
@@ -1421,15 +1463,14 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
                        break;
        }
 
-       //<2>Set PHY related register
+       /* <2> Set PHY related register */
        switch (priv->CurrentChannelBW) {
                case HT_CHANNEL_WIDTH_20:
-                       // Add by Vivi 20071119
                        rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x0);
                        rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x0);
                        rtl8192_setBBreg(dev, rFPGA0_AnalogParameter1, 0x00100000, 1);
 
-                       // Correct the tx power for CCK rate in 20M. Suggest by YN, 20071207
+                       /* Correct the tx power for CCK rate in 20M. */
                        priv->cck_present_attentuation =
                                priv->cck_present_attentuation_20Mdefault + priv->cck_present_attentuation_difference;
 
@@ -1451,7 +1492,6 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
 
                        break;
                case HT_CHANNEL_WIDTH_20_40:
-                       // Add by Vivi 20071119
                        rtl8192_setBBreg(dev, rFPGA0_RFMOD, bRFMOD, 0x1);
                        rtl8192_setBBreg(dev, rFPGA1_RFMOD, bRFMOD, 0x1);
                        rtl8192_setBBreg(dev, rCCK0_System, bCCKSideBand, (priv->nCur40MhzPrimeSC>>1));
@@ -1482,9 +1522,10 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
                        break;
 
        }
-       //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
+       /* Skip over setting of J-mode in BB register here.
+          Default value is "None J mode". */
 
-       //<3>Set RF related register
+       /* <3> Set RF related register */
        switch (priv->rf_chip) {
                case RF_8225:
 #ifdef TO_DO_LIST
@@ -1497,11 +1538,9 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
                        break;
 
                case RF_8258:
-                       // PHY_SetRF8258Bandwidth();
                        break;
 
                case RF_PSEUDO_11N:
-                       // Do Nothing
                        break;
 
                default:
@@ -1514,15 +1553,15 @@ void rtl8192_SetBWModeWorkItem(struct net_device *dev)
 }
 
 /******************************************************************************
- *function:  This function schedules bandwidth switch work.
- *   input:  struct net_device *dev
- *          HT_CHANNEL_WIDTH   bandwidth  //20M or 40M
- *          HT_EXTCHNL_OFFSET  offset     //Upper, Lower, or Don't care
- *  output:  none
- *  return:  none
- *    Note:  I doubt whether SetBWModeInProgress flag is necessary as we can
- *          test whether current work in the queue or not.//do I?
- * ***************************************************************************/
+ * function:  This function schedules bandwidth switch work.
+ * input:     struct net_deviceq   *dev
+ *            HT_CHANNEL_WIDTH     bandwidth  //20M or 40M
+ *            HT_EXTCHNL_OFFSET    offset     //Upper, Lower, or Don't care
+ * output:    none
+ * return:    none
+ * notice:    I doubt whether SetBWModeInProgress flag is necessary as we can
+ *           test whether current work in the queue or not.//do I?
+ *****************************************************************************/
 void rtl8192_SetBWMode(struct net_device *dev, HT_CHANNEL_WIDTH bandwidth,
                       HT_EXTCHNL_OFFSET offset)
 {
@@ -1574,7 +1613,8 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
                        initial_gain = SCAN_RX_INITIAL_GAIN;
                        bitmask = bMaskByte0;
                        if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
-                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
+                               /* FW DIG OFF */
+                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
                        priv->initgain_backup.xaagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XAAGCCore1, bitmask);
                        priv->initgain_backup.xbagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XBAGCCore1, bitmask);
                        priv->initgain_backup.xcagccore1 = (u8)rtl8192_QueryBBReg(dev, rOFDM0_XCAGCCore1, bitmask);
@@ -1598,9 +1638,10 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
                        break;
                case IG_Restore:
                        RT_TRACE(COMP_SCAN, "IG_Restore, restore the initial gain.\n");
-                       bitmask = 0x7f; //Bit0~ Bit6
+                       bitmask = 0x7f; /* Bit0 ~ Bit6 */
                        if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
-                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);   // FW DIG OFF
+                               /* FW DIG OFF */
+                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x8);
 
                        rtl8192_setBBreg(dev, rOFDM0_XAAGCCore1, bitmask, (u32)priv->initgain_backup.xaagccore1);
                        rtl8192_setBBreg(dev, rOFDM0_XBAGCCore1, bitmask, (u32)priv->initgain_backup.xbagccore1);
@@ -1624,7 +1665,8 @@ extern void InitialGainOperateWorkItemCallBack(struct work_struct *work)
                        rtl8192_phy_setTxPower(dev, priv->ieee80211->current_network.channel);
 
                        if (dm_digtable.dig_algorithm == DIG_ALGO_BY_FALSE_ALARM)
-                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);   // FW DIG ON
+                               /* FW DIG ON */
+                               rtl8192_setBBreg(dev, UFWP, bMaskByte1, 0x1);
                        break;
                default:
                        RT_TRACE(COMP_SCAN, "Unknown IG Operation. \n");