drm/i915/mtl: Add MTL performance tuning changes

MTL reuses the tuning parameters for DG2. Extend the dg2
performance tuning parameters to MTL.

v2: Add DRAW_WATERMARK tuning parameter.
v3: Limit DRAW_WATERMARK tuning to non A0 step.
v4: Reorder platform checks.
    Restrict Blend fill caching optimization to Render GT.
v5: Move mtl tuning params to its own function

Bspec: 68331
Cc: Haridhar Kalvala <haridhar.kalvala@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Gustavo Sousa <gustavo.sousa@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230517233111.297542-1-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 786349e..4d2dece 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -812,11 +812,25 @@ static void dg2_ctx_workarounds_init(struct intel_engine_cs *engine,
        wa_masked_en(wal, CACHE_MODE_1, MSAA_OPTIMIZATION_REDUC_DISABLE);
 }
 
+static void mtl_ctx_gt_tuning_init(struct intel_engine_cs *engine,
+                                  struct i915_wa_list *wal)
+{
+       struct drm_i915_private *i915 = engine->i915;
+
+       dg2_ctx_gt_tuning_init(engine, wal);
+
+       if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_B0, STEP_FOREVER) ||
+           IS_MTL_GRAPHICS_STEP(i915, P, STEP_B0, STEP_FOREVER))
+               wa_add(wal, DRAW_WATERMARK, VERT_WM_VAL, 0x3FF, 0, false);
+}
+
 static void mtl_ctx_workarounds_init(struct intel_engine_cs *engine,
                                     struct i915_wa_list *wal)
 {
        struct drm_i915_private *i915 = engine->i915;
 
+       mtl_ctx_gt_tuning_init(engine, wal);
+
        if (IS_MTL_GRAPHICS_STEP(i915, M, STEP_A0, STEP_B0) ||
            IS_MTL_GRAPHICS_STEP(i915, P, STEP_A0, STEP_B0)) {
                /* Wa_14014947963 */
@@ -1748,6 +1762,13 @@ xelpmp_gt_workarounds_init(struct intel_gt *gt, struct i915_wa_list *wal)
  */
 static void gt_tuning_settings(struct intel_gt *gt, struct i915_wa_list *wal)
 {
+       if (IS_METEORLAKE(gt->i915)) {
+               if (gt->type != GT_MEDIA)
+                       wa_mcr_write_or(wal, XEHP_L3SCQREG7, BLEND_FILL_CACHING_OPT_DIS);
+
+               wa_mcr_write_or(wal, XEHP_SQCM, EN_32B_ACCESS);
+       }
+
        if (IS_PONTEVECCHIO(gt->i915)) {
                wa_mcr_write(wal, XEHPC_L3SCRUB,
                             SCRUB_CL_DWNGRADE_SHARED | SCRUB_RATE_4B_PER_CLK);
@@ -2944,7 +2965,7 @@ static void
 add_render_compute_tuning_settings(struct drm_i915_private *i915,
                                   struct i915_wa_list *wal)
 {
-       if (IS_DG2(i915))
+       if (IS_METEORLAKE(i915) || IS_DG2(i915))
                wa_mcr_write_clr_set(wal, RT_CTRL, STACKID_CTRL, STACKID_CTRL_512);
 
        /*