#include <linux/timer.h>
 #include <linux/vmalloc.h>
 #include <linux/etherdevice.h>
+#include <linux/net_tstamp.h>
 #include <asm/io.h>
 #include "cxgb4_uld.h"
 
 #ifdef CONFIG_CHELSIO_T4_FCOE
        struct cxgb_fcoe fcoe;
 #endif /* CONFIG_CHELSIO_T4_FCOE */
+       bool rxtstamp;  /* Enable TS */
+       struct hwtstamp_config tstamp_config;
 };
 
 struct dentry;
 
 /* A packet gather list */
 struct pkt_gl {
+       u64 sgetstamp;              /* SGE Time Stamp for Ingress Packet */
        struct page_frag frags[MAX_SKB_FRAGS];
        void *va;                         /* virtual address of first byte */
        unsigned int nfrags;              /* # of fragments */
 
        return ret;
 }
 
+static int get_ts_info(struct net_device *dev, struct ethtool_ts_info *ts_info)
+{
+       ts_info->so_timestamping = SOF_TIMESTAMPING_TX_SOFTWARE |
+                                  SOF_TIMESTAMPING_RX_SOFTWARE |
+                                  SOF_TIMESTAMPING_SOFTWARE;
+
+       ts_info->so_timestamping |= SOF_TIMESTAMPING_RX_HARDWARE |
+                                   SOF_TIMESTAMPING_RAW_HARDWARE;
+
+       ts_info->phc_index = -1;
+
+       return 0;
+}
+
 static u32 get_rss_table_size(struct net_device *dev)
 {
        const struct port_info *pi = netdev_priv(dev);
        .get_rxfh          = get_rss_table,
        .set_rxfh          = set_rss_table,
        .flash_device      = set_flash,
+       .get_ts_info       = get_ts_info
 };
 
 void cxgb4_set_ethtool_ops(struct net_device *netdev)
 
                        ret = t4_mdio_wr(pi->adapter, mbox, prtad, devad,
                                         data->reg_num, data->val_in);
                break;
+       case SIOCGHWTSTAMP:
+               return copy_to_user(req->ifr_data, &pi->tstamp_config,
+                                   sizeof(pi->tstamp_config)) ?
+                       -EFAULT : 0;
+       case SIOCSHWTSTAMP:
+               if (copy_from_user(&pi->tstamp_config, req->ifr_data,
+                                  sizeof(pi->tstamp_config)))
+                       return -EFAULT;
+
+               switch (pi->tstamp_config.rx_filter) {
+               case HWTSTAMP_FILTER_NONE:
+                       pi->rxtstamp = false;
+                       break;
+               case HWTSTAMP_FILTER_ALL:
+                       pi->rxtstamp = true;
+                       break;
+               default:
+                       pi->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
+                       return -ERANGE;
+               }
+
+               return copy_to_user(req->ifr_data, &pi->tstamp_config,
+                                   sizeof(pi->tstamp_config)) ?
+                       -EFAULT : 0;
        default:
                return -EOPNOTSUPP;
        }
 
        return 0;
 }
 
+/**
+ * cxgb4_sgetim_to_hwtstamp - convert sge time stamp to hw time stamp
+ * @adap: the adapter
+ * @hwtstamps: time stamp structure to update
+ * @sgetstamp: 60bit iqe timestamp
+ *
+ * Every ingress queue entry has the 60-bit timestamp, convert that timestamp
+ * which is in Core Clock ticks into ktime_t and assign it
+ **/
+static void cxgb4_sgetim_to_hwtstamp(struct adapter *adap,
+                                    struct skb_shared_hwtstamps *hwtstamps,
+                                    u64 sgetstamp)
+{
+       u64 ns;
+       u64 tmp = (sgetstamp * 1000 * 1000 + adap->params.vpd.cclk / 2);
+
+       ns = div_u64(tmp, adap->params.vpd.cclk);
+
+       memset(hwtstamps, 0, sizeof(*hwtstamps));
+       hwtstamps->hwtstamp = ns_to_ktime(ns);
+}
+
 static void do_gro(struct sge_eth_rxq *rxq, const struct pkt_gl *gl,
                   const struct cpl_rx_pkt *pkt)
 {
        struct adapter *adapter = rxq->rspq.adap;
        struct sge *s = &adapter->sge;
+       struct port_info *pi;
        int ret;
        struct sk_buff *skb;
 
        skb->ip_summed = CHECKSUM_UNNECESSARY;
        skb_record_rx_queue(skb, rxq->rspq.idx);
        skb_mark_napi_id(skb, &rxq->rspq.napi);
+       pi = netdev_priv(skb->dev);
+       if (pi->rxtstamp)
+               cxgb4_sgetim_to_hwtstamp(adapter, skb_hwtstamps(skb),
+                                        gl->sgetstamp);
        if (rxq->rspq.netdev->features & NETIF_F_RXHASH)
                skb_set_hash(skb, (__force u32)pkt->rsshdr.hash_val,
                             PKT_HASH_TYPE_L3);
        struct sge *s = &q->adap->sge;
        int cpl_trace_pkt = is_t4(q->adap->params.chip) ?
                            CPL_TRACE_PKT : CPL_TRACE_PKT_T5;
-#ifdef CONFIG_CHELSIO_T4_FCOE
        struct port_info *pi;
-#endif
 
        if (unlikely(*(u8 *)rsp == cpl_trace_pkt))
                return handle_trace_pkt(q->adap, si);
 
        rxq->stats.pkts++;
 
+       pi = netdev_priv(skb->dev);
+       if (pi->rxtstamp)
+               cxgb4_sgetim_to_hwtstamp(q->adap, skb_hwtstamps(skb),
+                                        si->sgetstamp);
        if (csum_ok && (pkt->l2info & htonl(RXF_UDP_F | RXF_TCP_F))) {
                if (!pkt->ip_frag) {
                        skb->ip_summed = CHECKSUM_UNNECESSARY;
 #define CPL_RX_PKT_FLAGS (RXF_PSH_F | RXF_SYN_F | RXF_UDP_F | \
                          RXF_TCP_F | RXF_IP_F | RXF_IP6_F | RXF_LRO_F)
 
-               pi = netdev_priv(skb->dev);
                if (!(pkt->l2info & cpu_to_be32(CPL_RX_PKT_FLAGS))) {
                        if ((pkt->l2info & cpu_to_be32(RXF_FCOE_F)) &&
                            (pi->fcoe.flags & CXGB_FCOE_ENABLED)) {
                                unmap_rx_buf(q->adap, &rxq->fl);
                        }
 
+                       si.sgetstamp = SGE_TIMESTAMP_G(
+                                       be64_to_cpu(rc->last_flit));
                        /*
                         * Last buffer remains mapped so explicitly make it
                         * coherent for CPU access.