arm64: dts: Fix TPM schema violations
authorLukas Wunner <lukas@wunner.de>
Sat, 13 Jan 2024 18:06:56 +0000 (19:06 +0100)
committerArnd Bergmann <arnd@arndb.de>
Thu, 25 Jan 2024 17:10:07 +0000 (18:10 +0100)
Since commit 26c9d152ebf3 ("dt-bindings: tpm: Consolidate TCG TIS
bindings"), several issues are reported by "make dtbs_check" for arm64
devicetrees:

The compatible property needs to contain the chip's name in addition to
the generic "tcg,tpm_tis-spi" and the nodename needs to be "tpm@0"
rather than "cr50@0":

  tpm@1: compatible: ['tcg,tpm_tis-spi'] is too short
        from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#

  cr50@0: $nodename:0: 'cr50@0' does not match '^tpm(@[0-9a-f]+)?$'
        from schema $id: http://devicetree.org/schemas/tpm/google,cr50.yaml#

Fix these schema violations.

phyGATE-Tauri uses an Infineon SLB9670:
https://lore.kernel.org/all/ab45c82485fa272f74adf560cbb58ee60cc42689.camel@phytec.de/

Gateworks Venice uses an Atmel ATTPM20P:
https://trac.gateworks.com/wiki/tpm

Signed-off-by: Lukas Wunner <lukas@wunner.de>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
12 files changed:
arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts
arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi
arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi
arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts
arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi
arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts
arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi
arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi
arch/arm64/boot/dts/rockchip/rk3399-gru-bob.dts
arch/arm64/boot/dts/rockchip/rk3399-gru-scarlet.dtsi

index 968f475..27a9025 100644 (file)
        };
 
        tpm: tpm@1 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
                interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
                interrupt-parent = <&gpio2>;
                pinctrl-names = "default";
index 3f3f2a2..752caa3 100644 (file)
@@ -89,7 +89,7 @@
        status = "okay";
 
        tpm@1 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
                reg = <0x1>;
                spi-max-frequency = <36000000>;
        };
index 06fed93..2aa6c10 100644 (file)
        status = "okay";
 
        tpm@1 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
                reg = <0x1>;
                spi-max-frequency = <36000000>;
        };
index feae77e..a080574 100644 (file)
        status = "okay";
 
        tpm: tpm@0 {
-               compatible = "infineon,slb9670";
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
                reg = <0>;
                pinctrl-names = "default";
                pinctrl-0 = <&pinctrl_tpm>;
index c24587c..41c79d2 100644 (file)
        status = "okay";
 
        tpm@1 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
                reg = <0x1>;
                spi-max-frequency = <36000000>;
        };
index 628ffba..d5c400b 100644 (file)
        status = "okay";
 
        tpm@1 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
                reg = <0x1>;
                spi-max-frequency = <36000000>;
        };
index 9caf7ca..cae586c 100644 (file)
        status = "okay";
 
        tpm@0 {
-               compatible = "tcg,tpm_tis-spi";
+               compatible = "atmel,attpm20p", "tcg,tpm_tis-spi";
                reg = <0x0>;
                spi-max-frequency = <36000000>;
        };
index 6376417..d8cf1f2 100644 (file)
@@ -65,7 +65,7 @@
        status = "okay";
 
        tpm@0 {
-               compatible = "infineon,slb9670";
+               compatible = "infineon,slb9670", "tcg,tpm_tis-spi";
                reg = <0>;
                spi-max-frequency = <43000000>;
        };
index 5506de8..1b3396b 100644 (file)
        status = "okay";
        cs-gpios = <&pio 86 GPIO_ACTIVE_LOW>;
 
-       cr50@0 {
+       tpm@0 {
                compatible = "google,cr50";
                reg = <0>;
                spi-max-frequency = <1000000>;
index f228125..d87aab8 100644 (file)
        pinctrl-names = "default";
        pinctrl-0 = <&spi5_pins>;
 
-       cr50@0 {
+       tpm@0 {
                compatible = "google,cr50";
                reg = <0>;
                interrupts-extended = <&pio 171 IRQ_TYPE_EDGE_RISING>;
index 0f9cc04..1cba1d8 100644 (file)
@@ -70,7 +70,7 @@
 &spi0 {
        status = "okay";
 
-       cr50@0 {
+       tpm@0 {
                compatible = "google,cr50";
                reg = <0>;
                interrupt-parent = <&gpio0>;
index c5e7de6..5846a11 100644 (file)
@@ -706,7 +706,7 @@ camera: &i2c7 {
 &spi2 {
        status = "okay";
 
-       cr50@0 {
+       tpm@0 {
                compatible = "google,cr50";
                reg = <0>;
                interrupt-parent = <&gpio1>;