clk: eyeq: add EyeQ5 fixed factor clocks

Expose additional clocks on EyeQ5. Some indexes come from dt-bindings
headers, others are private to the driver.

Few clocks are early (of_clk_init() stage: core clocks and UART clock),
others can wait until platform device probe. The source for this list
is downstream Mobileye kernel and some internal documentation.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Link: https://lore.kernel.org/r/20241106-mbly-clk-v2-6-84cfefb3f485@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 85beec6..5429090 100644 (file)
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -436,6 +436,90 @@ static const struct eqc_pll eqc_eyeq5_plls[] = {
        { .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 },
 };
 
+enum {
+       /*
+        * EQ5C_PLL_CPU children.
+        * EQ5C_PER_OCC_PCI is the last clock exposed in dt-bindings.
+        */
+       EQ5C_CPU_OCC = EQ5C_PER_OCC_PCI + 1,
+       EQ5C_CPU_SI_CSS0,
+       EQ5C_CPU_CPC,
+       EQ5C_CPU_CM,
+       EQ5C_CPU_MEM,
+       EQ5C_CPU_OCC_ISRAM,
+       EQ5C_CPU_ISRAM,
+       EQ5C_CPU_OCC_DBU,
+       EQ5C_CPU_SI_DBU_TP,
+
+       /*
+        * EQ5C_PLL_VDI children.
+        */
+       EQ5C_VDI_OCC_VDI,
+       EQ5C_VDI_VDI,
+       EQ5C_VDI_OCC_CAN_SER,
+       EQ5C_VDI_CAN_SER,
+       EQ5C_VDI_I2C_SER,
+
+       /*
+        * EQ5C_PLL_PER children.
+        */
+       EQ5C_PER_PERIPH,
+       EQ5C_PER_CAN,
+       EQ5C_PER_TIMER,
+       EQ5C_PER_CCF,
+       EQ5C_PER_OCC_MJPEG,
+       EQ5C_PER_HSM,
+       EQ5C_PER_MJPEG,
+       EQ5C_PER_FCMU_A,
+};
+
+static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = {
+       /* EQ5C_PLL_CPU children */
+       { EQ5C_CPU_OCC,         "occ-cpu",      1, 1,   EQ5C_PLL_CPU },
+       { EQ5C_CPU_SI_CSS0,     "si-css0",      1, 1,   EQ5C_CPU_OCC },
+       { EQ5C_CPU_CORE0,       "core0",        1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_CORE1,       "core1",        1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_CORE2,       "core2",        1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_CORE3,       "core3",        1, 1,   EQ5C_CPU_SI_CSS0 },
+
+       /* EQ5C_PLL_PER children */
+       { EQ5C_PER_OCC,         "occ-periph",   1, 16,  EQ5C_PLL_PER },
+       { EQ5C_PER_UART,        "uart",         1, 1,   EQ5C_PER_OCC },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = {
+       /* EQ5C_PLL_CPU children */
+       { EQ5C_CPU_CPC,         "cpc",          1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_CM,          "cm",           1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_MEM,         "mem",          1, 1,   EQ5C_CPU_SI_CSS0 },
+       { EQ5C_CPU_OCC_ISRAM,   "occ-isram",    1, 2,   EQ5C_PLL_CPU },
+       { EQ5C_CPU_ISRAM,       "isram",        1, 1,   EQ5C_CPU_OCC_ISRAM },
+       { EQ5C_CPU_OCC_DBU,     "occ-dbu",      1, 10,  EQ5C_PLL_CPU },
+       { EQ5C_CPU_SI_DBU_TP,   "si-dbu-tp",    1, 1,   EQ5C_CPU_OCC_DBU },
+
+       /* EQ5C_PLL_VDI children */
+       { EQ5C_VDI_OCC_VDI,     "occ-vdi",      1, 2,   EQ5C_PLL_VDI },
+       { EQ5C_VDI_VDI,         "vdi",          1, 1,   EQ5C_VDI_OCC_VDI },
+       { EQ5C_VDI_OCC_CAN_SER, "occ-can-ser",  1, 16,  EQ5C_PLL_VDI },
+       { EQ5C_VDI_CAN_SER,     "can-ser",      1, 1,   EQ5C_VDI_OCC_CAN_SER },
+       { EQ5C_VDI_I2C_SER,     "i2c-ser",      1, 20,  EQ5C_PLL_VDI },
+
+       /* EQ5C_PLL_PER children */
+       { EQ5C_PER_PERIPH,      "periph",       1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_CAN,         "can",          1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_SPI,         "spi",          1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_I2C,         "i2c",          1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_TIMER,       "timer",        1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_GPIO,        "gpio",         1, 1,   EQ5C_PER_OCC },
+       { EQ5C_PER_EMMC,        "emmc-sys",     1, 10,  EQ5C_PLL_PER },
+       { EQ5C_PER_CCF,         "ccf-ctrl",     1, 4,   EQ5C_PLL_PER },
+       { EQ5C_PER_OCC_MJPEG,   "occ-mjpeg",    1, 2,   EQ5C_PLL_PER },
+       { EQ5C_PER_HSM,         "hsm",          1, 1,   EQ5C_PER_OCC_MJPEG },
+       { EQ5C_PER_MJPEG,       "mjpeg",        1, 1,   EQ5C_PER_OCC_MJPEG },
+       { EQ5C_PER_FCMU_A,      "fcmu-a",       1, 20,  EQ5C_PLL_PER },
+       { EQ5C_PER_OCC_PCI,     "occ-pci-sys",  1, 8,   EQ5C_PLL_PER },
+};
+
 static const struct eqc_div eqc_eyeq5_divs[] = {
        {
                .index = EQ5C_DIV_OSPI,
@@ -451,7 +535,11 @@ static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst
        .early_pll_count        = ARRAY_SIZE(eqc_eyeq5_early_plls),
        .early_plls             = eqc_eyeq5_early_plls,
 
-       .late_clk_count         = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs),
+       .early_fixed_factor_count       = ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
+       .early_fixed_factors            = eqc_eyeq5_early_fixed_factors,
+
+       .late_clk_count         = ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs) +
+                                 ARRAY_SIZE(eqc_eyeq5_fixed_factors),
 };
 
 static const struct eqc_match_data eqc_eyeq5_match_data = {
@@ -461,10 +549,14 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
        .div_count      = ARRAY_SIZE(eqc_eyeq5_divs),
        .divs           = eqc_eyeq5_divs,
 
+       .fixed_factor_count     = ARRAY_SIZE(eqc_eyeq5_fixed_factors),
+       .fixed_factors          = eqc_eyeq5_fixed_factors,
+
        .reset_auxdev_name = "reset",
        .pinctrl_auxdev_name = "pinctrl",
 
-       .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls),
+       .early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) +
+                          ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
 };
 
 static const struct eqc_pll eqc_eyeq6l_plls[] = {