drm/amd/pm: add SMU11 common deep sleep control interface
authorEvan Quan <evan.quan@amd.com>
Mon, 17 Aug 2020 08:05:10 +0000 (16:05 +0800)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 18 Aug 2020 22:21:56 +0000 (18:21 -0400)
Considering the same logic can be applied to Arcturus, Navi1X
and Sienna Cichlid.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/pm/inc/smu_v11_0.h
drivers/gpu/drm/amd/pm/swsmu/smu11/arcturus_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/navi10_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/sienna_cichlid_ppt.c
drivers/gpu/drm/amd/pm/swsmu/smu11/smu_v11_0.c

index c4743f8..2a3f1ee 100644 (file)
@@ -277,5 +277,8 @@ void smu_v11_0_init_gpu_metrics_v1_0(struct gpu_metrics_v1_0 *gpu_metrics);
 int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
                              bool enablement);
 
+int smu_v11_0_deep_sleep_control(struct smu_context *smu,
+                                bool enablement);
+
 #endif
 #endif
index aab83b9..8347b1f 100644 (file)
@@ -2392,6 +2392,7 @@ static const struct pptable_funcs arcturus_ppt_funcs = {
        .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
        .get_gpu_metrics = arcturus_get_gpu_metrics,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void arcturus_set_ppt_funcs(struct smu_context *smu)
index c968f05..72f3d68 100644 (file)
@@ -2661,6 +2661,7 @@ static const struct pptable_funcs navi10_ppt_funcs = {
        .get_gpu_metrics = navi10_get_gpu_metrics,
        .enable_mgpu_fan_boost = navi10_enable_mgpu_fan_boost,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void navi10_set_ppt_funcs(struct smu_context *smu)
index 45b9def..8ffa8b7 100644 (file)
@@ -2797,6 +2797,7 @@ static const struct pptable_funcs sienna_cichlid_ppt_funcs = {
        .get_gpu_metrics = sienna_cichlid_get_gpu_metrics,
        .enable_mgpu_fan_boost = sienna_cichlid_enable_mgpu_fan_boost,
        .gfx_ulv_control = smu_v11_0_gfx_ulv_control,
+       .deep_sleep_control = smu_v11_0_deep_sleep_control,
 };
 
 void sienna_cichlid_set_ppt_funcs(struct smu_context *smu)
index 3c98060..ec20e83 100644 (file)
@@ -1996,3 +1996,36 @@ int smu_v11_0_gfx_ulv_control(struct smu_context *smu,
 
        return ret;
 }
+
+int smu_v11_0_deep_sleep_control(struct smu_context *smu,
+                                bool enablement)
+{
+       struct amdgpu_device *adev = smu->adev;
+       int ret = 0;
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
+               ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
+               if (ret) {
+                       dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
+                       return ret;
+               }
+       }
+
+       return ret;
+}