drm/amdgpu/gmc10: remove dummy read workaround for newer chips
authorAlex Deucher <alexander.deucher@amd.com>
Fri, 16 Oct 2020 16:56:26 +0000 (12:56 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Wed, 21 Oct 2020 20:14:28 +0000 (16:14 -0400)
Sienna Cichlid and newer have a hw fix so no longer require
the workaround.

Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/gmc_v10_0.c

index f7a8417..40af176 100644 (file)
@@ -107,7 +107,8 @@ static int gmc_v10_0_process_interrupt(struct amdgpu_device *adev,
                 * be updated to avoid reading an incorrect value due to
                 * the new fast GRBM interface.
                 */
-               if (entry->vmid_src == AMDGPU_GFXHUB_0)
+               if ((entry->vmid_src == AMDGPU_GFXHUB_0) &&
+                   (adev->asic_type < CHIP_SIENNA_CICHLID))
                        RREG32(hub->vm_l2_pro_fault_status);
 
                status = RREG32(hub->vm_l2_pro_fault_status);
@@ -232,7 +233,8 @@ static void gmc_v10_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
         * Issue a dummy read to wait for the ACK register to be cleared
         * to avoid a false ACK due to the new fast GRBM interface.
         */
-       if (vmhub == AMDGPU_GFXHUB_0)
+       if ((vmhub == AMDGPU_GFXHUB_0) &&
+           (adev->asic_type < CHIP_SIENNA_CICHLID))
                RREG32_NO_KIQ(hub->vm_inv_eng0_req + hub->eng_distance * eng);
 
        /* Wait for ACK with a delay.*/