Merge tag 'drm-fixes-2021-04-23' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "Just some small i915 and amdgpu fixes this week, should be all until
  you open the merge window.

  amdgpu:
   - Fix gpuvm page table update issue
   - Modifier fixes
   - Register fix for dimgrey cavefish

  i915:
   - GVT's BDW regression fix for cmd parser
   - Fix modesetting in case of unexpected AUX timeouts"

* tag 'drm-fixes-2021-04-23' of git://anongit.freedesktop.org/drm/drm:
  drm/amdgpu: fix GCR_GENERAL_CNTL offset for dimgrey_cavefish
  amd/display: allow non-linear multi-planar formats
  drm/amd/display: Update modifier list for gfx10_3
  drm/amdgpu: reserve fence slot to update page table
  drm/i915: Fix modesetting in case of unexpected AUX timeouts
  drm/i915/gvt: Fix BDW command parser regression

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 7d2c8b1..326dae3 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -3300,7 +3300,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
        struct amdgpu_bo *root;
        uint64_t value, flags;
        struct amdgpu_vm *vm;
-       long r;
+       int r;
 
        spin_lock(&adev->vm_manager.pasid_lock);
        vm = idr_find(&adev->vm_manager.pasid_idr, pasid);
@@ -3349,6 +3349,12 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
                value = 0;
        }
 
+       r = dma_resv_reserve_shared(root->tbo.base.resv, 1);
+       if (r) {
+               pr_debug("failed %d to reserve fence slot\n", r);
+               goto error_unlock;
+       }
+
        r = amdgpu_vm_bo_update_mapping(adev, adev, vm, true, false, NULL, addr,
                                        addr, flags, value, NULL, NULL,
                                        NULL);
@@ -3360,7 +3366,7 @@ bool amdgpu_vm_handle_fault(struct amdgpu_device *adev, u32 pasid,
 error_unlock:
        amdgpu_bo_unreserve(root);
        if (r < 0)
-               DRM_ERROR("Can't handle page fault (%ld)\n", r);
+               DRM_ERROR("Can't handle page fault (%d)\n", r);
 
 error_unref:
        amdgpu_bo_unref(&root);

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
index 45d1172..63691de 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c
@@ -3280,7 +3280,7 @@ static const struct soc15_reg_golden golden_settings_gc_10_3_4[] =
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_GCR_CNTL, 0x0007ffff, 0x0000c000),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG3, 0x00000280, 0x00000280),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG4, 0x07800000, 0x00800000),
-       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL, 0x00001d00, 0x00000500),
+       SOC15_REG_GOLDEN_VALUE(GC, 0, mmGCR_GENERAL_CNTL_Sienna_Cichlid, 0x00001d00, 0x00000500),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGE_PC_CNTL, 0x003c0000, 0x00280400),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),
        SOC15_REG_GOLDEN_VALUE(GC, 0, mmGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xffffffcf),

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 573cf17..d699a5c 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -4071,13 +4071,6 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
        if (modifier == DRM_FORMAT_MOD_LINEAR)
                return true;
 
-       /*
-        * The arbitrary tiling support for multiplane formats has not been hooked
-        * up.
-        */
-       if (info->num_planes > 1)
-               return false;
-
        /*
         * For D swizzle the canonical modifier depends on the bpp, so check
         * it here.
@@ -4096,6 +4089,10 @@ static bool dm_plane_format_mod_supported(struct drm_plane *plane,
                /* Per radeonsi comments 16/64 bpp are more complicated. */
                if (info->cpp[0] != 4)
                        return false;
+               /* We support multi-planar formats, but not when combined with
+                * additional DCC metadata planes. */
+               if (info->num_planes > 1)
+                       return false;
        }
 
        return true;
@@ -4296,7 +4293,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
                    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
                    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
                    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
-                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
 
        add_modifier(mods, size, capacity, AMD_FMT_MOD |
                    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |
@@ -4308,7 +4305,7 @@ add_gfx10_3_modifiers(const struct amdgpu_device *adev,
                    AMD_FMT_MOD_SET(DCC_CONSTANT_ENCODE, 1) |
                    AMD_FMT_MOD_SET(DCC_INDEPENDENT_64B, 1) |
                    AMD_FMT_MOD_SET(DCC_INDEPENDENT_128B, 1) |
-                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_128B));
+                   AMD_FMT_MOD_SET(DCC_MAX_COMPRESSED_BLOCK, AMD_FMT_MOD_DCC_BLOCK_64B));
 
        add_modifier(mods, size, capacity, AMD_FMT_MOD |
                    AMD_FMT_MOD_SET(TILE, AMD_FMT_MOD_TILE_GFX9_64K_R_X) |

diff --git a/drivers/gpu/drm/i915/display/intel_dp_link_training.c b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
index be6ac0d..2ed3095 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_link_training.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_link_training.c
@@ -848,7 +848,8 @@ void intel_dp_start_link_train(struct intel_dp *intel_dp,
        int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
 
        if (lttpr_count < 0)
-               return;
+               /* Still continue with enabling the port and link training. */
+               lttpr_count = 0;
 
        if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
                intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);

diff --git a/drivers/gpu/drm/i915/gvt/cmd_parser.c b/drivers/gpu/drm/i915/gvt/cmd_parser.c
index fef1e85..01c1d1b 100644 (file)
--- a/drivers/gpu/drm/i915/gvt/cmd_parser.c
+++ b/drivers/gpu/drm/i915/gvt/cmd_parser.c
@@ -916,19 +916,26 @@ static int cmd_reg_handler(struct parser_exec_state *s,
 
        if (!strncmp(cmd, "srm", 3) ||
                        !strncmp(cmd, "lrm", 3)) {
-               if (offset != i915_mmio_reg_offset(GEN8_L3SQCREG4) &&
-                               offset != 0x21f0) {
+               if (offset == i915_mmio_reg_offset(GEN8_L3SQCREG4) ||
+                   offset == 0x21f0 ||
+                   (IS_BROADWELL(gvt->gt->i915) &&
+                    offset == i915_mmio_reg_offset(INSTPM)))
+                       return 0;
+               else {
                        gvt_vgpu_err("%s access to register (%x)\n",
                                        cmd, offset);
                        return -EPERM;
-               } else
-                       return 0;
+               }
        }
 
        if (!strncmp(cmd, "lrr-src", 7) ||
                        !strncmp(cmd, "lrr-dst", 7)) {
-               gvt_vgpu_err("not allowed cmd %s\n", cmd);
-               return -EPERM;
+               if (IS_BROADWELL(gvt->gt->i915) && offset == 0x215c)
+                       return 0;
+               else {
+                       gvt_vgpu_err("not allowed cmd %s reg (%x)\n", cmd, offset);
+                       return -EPERM;
+               }
        }
 
        if (!strncmp(cmd, "pipe_ctrl", 9)) {