drm/amd/display: ensure dtbclk clk_src selected before hdmistream_clk_en
authorCharlene Liu <Charlene.Liu@amd.com>
Wed, 24 Jun 2026 22:54:43 +0000 (18:54 -0400)
committerAlex Deucher <alexander.deucher@amd.com>
Tue, 14 Jul 2026 23:12:35 +0000 (19:12 -0400)
[why]
correct a sequence issue by switching to dcn35's dccg sequence:
to make sure select dtbclk src first before programming hdmistream_clk_en.

Reviewed-by: Leo Chen <leo.chen@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
drivers/gpu/drm/amd/display/dc/dccg/dcn42/dcn42_dccg.c

index 483cd9a..617f504 100644 (file)
@@ -1654,7 +1654,7 @@ void dccg35_set_dpstreamclk_root_clock_gating(struct dccg *dccg, int dp_hpo_inst
 
 
 
-static void dccg35_set_hdmistreamclk(
+void dccg35_set_hdmistreamclk(
                struct dccg *dccg,
                enum streamclk_source src,
                uint32_t otg_inst)
index 5547002..58f4c1e 100644 (file)
@@ -269,5 +269,8 @@ void dccg35_disable_dscclk(struct dccg *dccg, int inst);
 
 void dccg35_enable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);
 void dccg35_disable_symclk_se(struct dccg *dccg, uint32_t stream_enc_inst, uint32_t link_enc_inst);
-
+void dccg35_set_hdmistreamclk(
+               struct dccg *dccg,
+               enum streamclk_source src,
+               uint32_t otg_inst);
 #endif //__DCN35_DCCG_H__
index 616a896..3b03b15 100644 (file)
@@ -313,7 +313,7 @@ static void dccg42_init(struct dccg *dccg)
 static const struct dccg_funcs dccg42_funcs = {
        .enable_hdmicharclk = dccg401_enable_hdmicharclk,
        .disable_hdmicharclk = dccg42_disable_hdmicharclk,
-       .set_hdmistreamclk = dccg401_set_hdmistreamclk,
+       .set_hdmistreamclk = dccg35_set_hdmistreamclk,
        .set_hdmistreamclk_root_clock_gating = dccg35_set_hdmistreamclk_root_clock_gating,
        .update_dpp_dto = dccg35_update_dpp_dto,
        .dpp_root_clock_control = dccg35_dpp_root_clock_control,