drm/i915: pass dev_priv explicitly to PIPE_WGC_C02

Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the PIPE_WGC_C02 register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/550d4e787445802236f0bf89e4d2f4f32cbd6d75.1714399071.git.jani.nikula@intel.com
Signed-off-by: Jani Nikula <jani.nikula@intel.com>

diff --git a/drivers/gpu/drm/i915/display/intel_color.c b/drivers/gpu/drm/i915/display/intel_color.c
index cdcf8e7..f96d6af 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color.c
+++ b/drivers/gpu/drm/i915/display/intel_color.c
@@ -618,7 +618,7 @@ static void vlv_load_wgc_csc(struct intel_crtc *crtc,
 
        intel_de_write_fw(dev_priv, PIPE_WGC_C01_C00(dev_priv, pipe),
                          csc->coeff[1] << 16 | csc->coeff[0]);
-       intel_de_write_fw(dev_priv, PIPE_WGC_C02(pipe),
+       intel_de_write_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe),
                          csc->coeff[2]);
 
        intel_de_write_fw(dev_priv, PIPE_WGC_C11_C10(pipe),
@@ -643,7 +643,7 @@ static void vlv_read_wgc_csc(struct intel_crtc *crtc,
        csc->coeff[0] = tmp & 0xffff;
        csc->coeff[1] = tmp >> 16;
 
-       tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(pipe));
+       tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C02(dev_priv, pipe));
        csc->coeff[2] = tmp & 0xffff;
 
        tmp = intel_de_read_fw(dev_priv, PIPE_WGC_C11_C10(pipe));

diff --git a/drivers/gpu/drm/i915/display/intel_color_regs.h b/drivers/gpu/drm/i915/display/intel_color_regs.h
index 5743898..741c0b8 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_color_regs.h
+++ b/drivers/gpu/drm/i915/display/intel_color_regs.h
@@ -257,7 +257,7 @@
 #define _PIPE_A_WGC_C22                0x600C4 /* s2.10 */
 
 #define PIPE_WGC_C01_C00(dev_priv, pipe)               _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C01_C00)
-#define PIPE_WGC_C02(pipe)             _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
+#define PIPE_WGC_C02(dev_priv, pipe)           _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C02)
 #define PIPE_WGC_C11_C10(pipe)         _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C11_C10)
 #define PIPE_WGC_C12(pipe)             _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C12)
 #define PIPE_WGC_C21_C20(pipe)         _MMIO_TRANS2(dev_priv, pipe, _PIPE_A_WGC_C21_C20)