drm/armada: add and use definitions for RDREG4F

Add and use bit definitions for RDREG4F on Dove Armada 510.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>

diff --git a/drivers/gpu/drm/armada/armada_510.c b/drivers/gpu/drm/armada/armada_510.c
index 0e91d27..370c422 100644 (file)
--- a/drivers/gpu/drm/armada/armada_510.c
+++ b/drivers/gpu/drm/armada/armada_510.c
@@ -24,8 +24,13 @@ static int armada510_crtc_init(struct armada_crtc *dcrtc, struct device *dev)
 
        dcrtc->extclk[0] = clk;
 
-       /* Lower the watermark so to eliminate jitter at higher bandwidths */
-       armada_updatel(0x20, (1 << 11) | 0xff, dcrtc->base + LCD_CFG_RDREG4F);
+       /*
+        * Lower the watermark so to eliminate jitter at higher bandwidths.
+        * Disable SRAM read wait state to avoid system hang with external
+        * clock.
+        */
+       armada_updatel(CFG_DMA_WM(0x20), CFG_SRAM_WAIT | CFG_DMA_WM_MASK,
+                      dcrtc->base + LCD_CFG_RDREG4F);
 
        /* Initialise SPU register */
        writel_relaxed(ADV_HWC32ENABLE | ADV_HWC32ARGB | ADV_HWC32BLEND,

diff --git a/drivers/gpu/drm/armada/armada_hw.h b/drivers/gpu/drm/armada/armada_hw.h
index babfca7..5b1af0c 100644 (file)
--- a/drivers/gpu/drm/armada/armada_hw.h
+++ b/drivers/gpu/drm/armada/armada_hw.h
@@ -88,6 +88,16 @@ enum {
        ADV_VSYNC_H_OFF = 0xfff << 0,
 };
 
+/* LCD_CFG_RDREG4F - Armada 510 only */
+enum {
+       CFG_SRAM_WAIT   = BIT(11),
+       CFG_SMPN_FASTTX = BIT(10),
+       CFG_DMA_ARB     = BIT(9),
+       CFG_DMA_WM_EN   = BIT(8),
+       CFG_DMA_WM_MASK = 0xff,
+#define CFG_DMA_WM(x)  ((x) & CFG_DMA_WM_MASK)
+};
+
 enum {
        CFG_565         = 0,
        CFG_1555        = 1,