drm/amdgpu: fix NAK-G generation during PCI-e link width switch

A lot of NAK-G being generated when link widht switching is happening.
WA for this issue is to program the SPC to 4 symbols per clock during
bootup when the native PCIE width is x4.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
index 25ee535..43d074b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.h
@@ -93,6 +93,7 @@ struct amdgpu_nbio_funcs {
        void (*enable_aspm)(struct amdgpu_device *adev,
                            bool enable);
        void (*program_aspm)(struct amdgpu_device *adev);
+       void (*apply_lc_spc_mode_wa)(struct amdgpu_device *adev);
 };
 
 struct amdgpu_nbio {

diff --git a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
index 05ddec7..315d57b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
+++ b/drivers/gpu/drm/amd/amdgpu/nbio_v2_3.c
@@ -51,6 +51,8 @@
 #define mmBIF_MMSCH1_DOORBELL_RANGE            0x01d8
 #define mmBIF_MMSCH1_DOORBELL_RANGE_BASE_IDX   2
 
+#define smnPCIE_LC_LINK_WIDTH_CNTL             0x11140288
+
 static void nbio_v2_3_remap_hdp_registers(struct amdgpu_device *adev)
 {
        WREG32_SOC15(NBIO, 0, mmREMAP_HDP_MEM_FLUSH_CNTL,
@@ -463,6 +465,31 @@ static void nbio_v2_3_program_aspm(struct amdgpu_device *adev)
                WREG32_PCIE(smnPCIE_LC_CNTL3, data);
 }
 
+static void nbio_v2_3_apply_lc_spc_mode_wa(struct amdgpu_device *adev)
+{
+       uint32_t reg_data = 0;
+       uint32_t link_width = 0;
+
+       if (!((adev->asic_type >= CHIP_NAVI10) &&
+            (adev->asic_type <= CHIP_NAVI12)))
+               return;
+
+       reg_data = RREG32_PCIE(smnPCIE_LC_LINK_WIDTH_CNTL);
+       link_width = (reg_data & PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD_MASK)
+               >> PCIE_LC_LINK_WIDTH_CNTL__LC_LINK_WIDTH_RD__SHIFT;
+
+       /*
+        * Program PCIE_LC_CNTL6.LC_SPC_MODE_8GT to 0x2 (4 symbols per clock data)
+        * if link_width is 0x3 (x4)
+        */
+       if (0x3 == link_width) {
+               reg_data = RREG32_PCIE(smnPCIE_LC_CNTL6);
+               reg_data &= ~PCIE_LC_CNTL6__LC_SPC_MODE_8GT_MASK;
+               reg_data |= (0x2 << PCIE_LC_CNTL6__LC_SPC_MODE_8GT__SHIFT);
+               WREG32_PCIE(smnPCIE_LC_CNTL6, reg_data);
+       }
+}
+
 const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
        .get_hdp_flush_req_offset = nbio_v2_3_get_hdp_flush_req_offset,
        .get_hdp_flush_done_offset = nbio_v2_3_get_hdp_flush_done_offset,
@@ -484,4 +511,5 @@ const struct amdgpu_nbio_funcs nbio_v2_3_funcs = {
        .remap_hdp_registers = nbio_v2_3_remap_hdp_registers,
        .enable_aspm = nbio_v2_3_enable_aspm,
        .program_aspm =  nbio_v2_3_program_aspm,
+       .apply_lc_spc_mode_wa = nbio_v2_3_apply_lc_spc_mode_wa,
 };

diff --git a/drivers/gpu/drm/amd/amdgpu/nv.c b/drivers/gpu/drm/amd/amdgpu/nv.c
index 455d042..63c96ca 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/nv.c
+++ b/drivers/gpu/drm/amd/amdgpu/nv.c
@@ -1411,6 +1411,9 @@ static int nv_common_hw_init(void *handle)
 {
        struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 
+       if (adev->nbio.funcs->apply_lc_spc_mode_wa)
+               adev->nbio.funcs->apply_lc_spc_mode_wa(adev);
+
        /* enable pcie gen2/3 link */
        nv_pcie_gen3_enable(adev);
        /* enable aspm */