drm/amd/display: Fix indenting of dpms on

[Why & How]
Cleanup for future refactors.

Reviewed-by: Wenjing Liu <wenjing.liu@amd.com>
Signed-off-by: Dominik Kaszewski <dominik.kaszewski@amd.com>
Signed-off-by: George Zhang <george.zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
index 479a8fb..335ae95 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
+++ b/drivers/gpu/drm/amd/display/dc/link/link_dpms.c
@@ -2610,13 +2610,14 @@ void link_set_dpms_on(
         */
        if (stream->timing.flags.DSC) {
                if (dc_is_dp_signal(stream->signal) ||
-                   dc_is_virtual_signal(stream->signal))
+                       dc_is_virtual_signal(stream->signal))
                        link_set_dsc_enable(pipe_ctx, true);
        }
 
        if (link->replay_settings.config.replay_supported && !dc_is_embedded_signal(link->connector_signal))
                dp_setup_replay(link, stream);
 
+       // TODO: Split DPMS-on into 3 functions at this point
        status = enable_link(state, pipe_ctx);
 
        if (status != DC_OK) {
@@ -2629,9 +2630,9 @@ void link_set_dpms_on(
                 * show the stream anyway. But MST displays can't proceed
                 * without link training.
                 */
-                       if ((status != DC_FAIL_DP_LINK_TRAINING &&
-                                       status != DC_FAIL_HDMI_FRL_LINK_TRAINING) ||
-                                       stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
+               if ((status != DC_FAIL_DP_LINK_TRAINING &&
+                               status != DC_FAIL_HDMI_FRL_LINK_TRAINING) ||
+                               stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST) {
                        if (false == link->link_status.link_active)
                                disable_link(link, &pipe_ctx->link_res,
                                                stream->signal);
@@ -2639,6 +2640,7 @@ void link_set_dpms_on(
                        return;
                }
        }
+       // TODO: Split DPMS-on into 3 functions at this point
 
        if (stream->timing.flags.DSC && dc_is_hdmi_frl_signal(stream->signal))
                //TODO: bring HDMI FRL in line with DP
@@ -2657,13 +2659,11 @@ void link_set_dpms_on(
        if (!(dc_is_virtual_signal(stream->signal) ||
                        dc_is_hdmi_frl_signal(stream->signal) ||
                        dp_is_128b_132b_signal(pipe_ctx))) {
-
-                       if (link_enc)
-                               link_enc->funcs->setup(
+               if (link_enc)
+                       link_enc->funcs->setup(
                                        link_enc,
                                        stream->signal);
-
-               }
+       }
 
        dc->hwss.enable_stream(pipe_ctx);