clk: core: replace clk_{readl,writel} with {readl,writel}

Now that clk_{readl,writel} is just an alias for {readl,writel}, we can
switch all users of clk_* to use the accessors directly and remove the
helpers.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
[sboyd@kernel.org: Also convert renesas file so that this can be
compile independently]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 32f93dc..46852e9 100644 (file)
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -30,7 +30,7 @@ static inline u32 clk_div_readl(struct clk_divider *divider)
        if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
                return ioread32be(divider->reg);
 
-       return clk_readl(divider->reg);
+       return readl(divider->reg);
 }
 
 static inline void clk_div_writel(struct clk_divider *divider, u32 val)
@@ -38,7 +38,7 @@ static inline void clk_div_writel(struct clk_divider *divider, u32 val)
        if (divider->flags & CLK_DIVIDER_BIG_ENDIAN)
                iowrite32be(val, divider->reg);
        else
-               clk_writel(val, divider->reg);
+               writel(val, divider->reg);
 }
 
 static unsigned int _get_table_maxdiv(const struct clk_div_table *table,

diff --git a/drivers/clk/clk-fractional-divider.c b/drivers/clk/clk-fractional-divider.c
index f88df26..638a9bb 100644 (file)
--- a/drivers/clk/clk-fractional-divider.c
+++ b/drivers/clk/clk-fractional-divider.c
@@ -18,7 +18,7 @@ static inline u32 clk_fd_readl(struct clk_fractional_divider *fd)
        if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
                return ioread32be(fd->reg);
 
-       return clk_readl(fd->reg);
+       return readl(fd->reg);
 }
 
 static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
@@ -26,7 +26,7 @@ static inline void clk_fd_writel(struct clk_fractional_divider *fd, u32 val)
        if (fd->flags & CLK_FRAC_DIVIDER_BIG_ENDIAN)
                iowrite32be(val, fd->reg);
        else
-               clk_writel(val, fd->reg);
+               writel(val, fd->reg);
 }
 
 static unsigned long clk_fd_recalc_rate(struct clk_hw *hw,

diff --git a/drivers/clk/clk-gate.c b/drivers/clk/clk-gate.c
index 6ced7b1..0c0bb83 100644 (file)
--- a/drivers/clk/clk-gate.c
+++ b/drivers/clk/clk-gate.c
@@ -28,7 +28,7 @@ static inline u32 clk_gate_readl(struct clk_gate *gate)
        if (gate->flags & CLK_GATE_BIG_ENDIAN)
                return ioread32be(gate->reg);
 
-       return clk_readl(gate->reg);
+       return readl(gate->reg);
 }
 
 static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
@@ -36,7 +36,7 @@ static inline void clk_gate_writel(struct clk_gate *gate, u32 val)
        if (gate->flags & CLK_GATE_BIG_ENDIAN)
                iowrite32be(val, gate->reg);
        else
-               clk_writel(val, gate->reg);
+               writel(val, gate->reg);
 }
 
 /*

diff --git a/drivers/clk/clk-multiplier.c b/drivers/clk/clk-multiplier.c
index 77327df..94470b4 100644 (file)
--- a/drivers/clk/clk-multiplier.c
+++ b/drivers/clk/clk-multiplier.c
@@ -16,7 +16,7 @@ static inline u32 clk_mult_readl(struct clk_multiplier *mult)
        if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
                return ioread32be(mult->reg);
 
-       return clk_readl(mult->reg);
+       return readl(mult->reg);
 }
 
 static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
@@ -24,7 +24,7 @@ static inline void clk_mult_writel(struct clk_multiplier *mult, u32 val)
        if (mult->flags & CLK_MULTIPLIER_BIG_ENDIAN)
                iowrite32be(val, mult->reg);
        else
-               clk_writel(val, mult->reg);
+               writel(val, mult->reg);
 }
 
 static unsigned long __get_mult(struct clk_multiplier *mult,

diff --git a/drivers/clk/clk-mux.c b/drivers/clk/clk-mux.c
index 61ad331..893c9b2 100644 (file)
--- a/drivers/clk/clk-mux.c
+++ b/drivers/clk/clk-mux.c
@@ -28,7 +28,7 @@ static inline u32 clk_mux_readl(struct clk_mux *mux)
        if (mux->flags & CLK_MUX_BIG_ENDIAN)
                return ioread32be(mux->reg);
 
-       return clk_readl(mux->reg);
+       return readl(mux->reg);
 }
 
 static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
@@ -36,7 +36,7 @@ static inline void clk_mux_writel(struct clk_mux *mux, u32 val)
        if (mux->flags & CLK_MUX_BIG_ENDIAN)
                iowrite32be(val, mux->reg);
        else
-               clk_writel(val, mux->reg);
+               writel(val, mux->reg);
 }
 
 int clk_mux_val_to_index(struct clk_hw *hw, u32 *table, unsigned int flags,

diff --git a/drivers/clk/clk-xgene.c b/drivers/clk/clk-xgene.c
index 531b030..d975465 100644 (file)
--- a/drivers/clk/clk-xgene.c
+++ b/drivers/clk/clk-xgene.c
@@ -262,7 +262,7 @@ static unsigned long xgene_clk_pmd_recalc_rate(struct clk_hw *hw,
        else
                __acquire(fd->lock);
 
-       val = clk_readl(fd->reg);
+       val = readl(fd->reg);
 
        if (fd->lock)
                spin_unlock_irqrestore(fd->lock, flags);
@@ -333,10 +333,10 @@ static int xgene_clk_pmd_set_rate(struct clk_hw *hw, unsigned long rate,
        else
                __acquire(fd->lock);
 
-       val = clk_readl(fd->reg);
+       val = readl(fd->reg);
        val &= ~fd->mask;
        val |= (scale << fd->shift);
-       clk_writel(val, fd->reg);
+       writel(val, fd->reg);
 
        if (fd->lock)
                spin_unlock_irqrestore(fd->lock, flags);

diff --git a/drivers/clk/hisilicon/clk-hisi-phase.c b/drivers/clk/hisilicon/clk-hisi-phase.c
index 5fdc267..ba6afad 100644 (file)
--- a/drivers/clk/hisilicon/clk-hisi-phase.c
+++ b/drivers/clk/hisilicon/clk-hisi-phase.c
@@ -75,10 +75,10 @@ static int hisi_clk_set_phase(struct clk_hw *hw, int degrees)
 
        spin_lock_irqsave(phase->lock, flags);
 
-       val = clk_readl(phase->reg);
+       val = readl(phase->reg);
        val &= ~phase->mask;
        val |= regval << phase->shift;
-       clk_writel(val, phase->reg);
+       writel(val, phase->reg);
 
        spin_unlock_irqrestore(phase->lock, flags);
 

diff --git a/drivers/clk/imx/clk-divider-gate.c b/drivers/clk/imx/clk-divider-gate.c
index df1f842..2a8352a 100644 (file)
--- a/drivers/clk/imx/clk-divider-gate.c
+++ b/drivers/clk/imx/clk-divider-gate.c
@@ -29,7 +29,7 @@ static unsigned long clk_divider_gate_recalc_rate_ro(struct clk_hw *hw,
        struct clk_divider *div = to_clk_divider(hw);
        unsigned int val;
 
-       val = clk_readl(div->reg) >> div->shift;
+       val = readl(div->reg) >> div->shift;
        val &= clk_div_mask(div->width);
        if (!val)
                return 0;
@@ -51,7 +51,7 @@ static unsigned long clk_divider_gate_recalc_rate(struct clk_hw *hw,
        if (!clk_hw_is_enabled(hw)) {
                val = div_gate->cached_val;
        } else {
-               val = clk_readl(div->reg) >> div->shift;
+               val = readl(div->reg) >> div->shift;
                val &= clk_div_mask(div->width);
        }
 
@@ -87,10 +87,10 @@ static int clk_divider_gate_set_rate(struct clk_hw *hw, unsigned long rate,
        spin_lock_irqsave(div->lock, flags);
 
        if (clk_hw_is_enabled(hw)) {
-               val = clk_readl(div->reg);
+               val = readl(div->reg);
                val &= ~(clk_div_mask(div->width) << div->shift);
                val |= (u32)value << div->shift;
-               clk_writel(val, div->reg);
+               writel(val, div->reg);
        } else {
                div_gate->cached_val = value;
        }
@@ -114,9 +114,9 @@ static int clk_divider_enable(struct clk_hw *hw)
 
        spin_lock_irqsave(div->lock, flags);
        /* restore div val */
-       val = clk_readl(div->reg);
+       val = readl(div->reg);
        val |= div_gate->cached_val << div->shift;
-       clk_writel(val, div->reg);
+       writel(val, div->reg);
 
        spin_unlock_irqrestore(div->lock, flags);
 
@@ -133,10 +133,10 @@ static void clk_divider_disable(struct clk_hw *hw)
        spin_lock_irqsave(div->lock, flags);
 
        /* store the current div val */
-       val = clk_readl(div->reg) >> div->shift;
+       val = readl(div->reg) >> div->shift;
        val &= clk_div_mask(div->width);
        div_gate->cached_val = val;
-       clk_writel(0, div->reg);
+       writel(0, div->reg);
 
        spin_unlock_irqrestore(div->lock, flags);
 }
@@ -146,7 +146,7 @@ static int clk_divider_is_enabled(struct clk_hw *hw)
        struct clk_divider *div = to_clk_divider(hw);
        u32 val;
 
-       val = clk_readl(div->reg) >> div->shift;
+       val = readl(div->reg) >> div->shift;
        val &= clk_div_mask(div->width);
 
        return val ? 1 : 0;
@@ -206,7 +206,7 @@ struct clk_hw *imx_clk_divider_gate(const char *name, const char *parent_name,
        div_gate->divider.hw.init = &init;
        div_gate->divider.flags = CLK_DIVIDER_ONE_BASED | clk_divider_flags;
        /* cache gate status */
-       val = clk_readl(reg) >> shift;
+       val = readl(reg) >> shift;
        val &= clk_div_mask(width);
        div_gate->cached_val = val;
 

diff --git a/drivers/clk/imx/clk-sccg-pll.c b/drivers/clk/imx/clk-sccg-pll.c
index 9dfd03a..991bbe6 100644 (file)
--- a/drivers/clk/imx/clk-sccg-pll.c
+++ b/drivers/clk/imx/clk-sccg-pll.c
@@ -348,7 +348,7 @@ static unsigned long clk_sccg_pll_recalc_rate(struct clk_hw *hw,
 
        temp64 = parent_rate;
 
-       val = clk_readl(pll->base + PLL_CFG0);
+       val = readl(pll->base + PLL_CFG0);
        if (val & SSCG_PLL_BYPASS2_MASK) {
                temp64 = parent_rate;
        } else if (val & SSCG_PLL_BYPASS1_MASK) {
@@ -371,10 +371,10 @@ static int clk_sccg_pll_set_rate(struct clk_hw *hw, unsigned long rate,
        u32 val;
 
        /* set bypass here too since the parent might be the same */
-       val = clk_readl(pll->base + PLL_CFG0);
+       val = readl(pll->base + PLL_CFG0);
        val &= ~SSCG_PLL_BYPASS_MASK;
        val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, setup->bypass);
-       clk_writel(val, pll->base + PLL_CFG0);
+       writel(val, pll->base + PLL_CFG0);
 
        val = readl_relaxed(pll->base + PLL_CFG2);
        val &= ~(PLL_DIVF1_MASK | PLL_DIVF2_MASK);
@@ -395,7 +395,7 @@ static u8 clk_sccg_pll_get_parent(struct clk_hw *hw)
        u32 val;
        u8 ret = pll->parent;
 
-       val = clk_readl(pll->base + PLL_CFG0);
+       val = readl(pll->base + PLL_CFG0);
        if (val & SSCG_PLL_BYPASS2_MASK)
                ret = pll->bypass2;
        else if (val & SSCG_PLL_BYPASS1_MASK)
@@ -408,10 +408,10 @@ static int clk_sccg_pll_set_parent(struct clk_hw *hw, u8 index)
        struct clk_sccg_pll *pll = to_clk_sccg_pll(hw);
        u32 val;
 
-       val = clk_readl(pll->base + PLL_CFG0);
+       val = readl(pll->base + PLL_CFG0);
        val &= ~SSCG_PLL_BYPASS_MASK;
        val |= FIELD_PREP(SSCG_PLL_BYPASS_MASK, pll->setup.bypass);
-       clk_writel(val, pll->base + PLL_CFG0);
+       writel(val, pll->base + PLL_CFG0);
 
        return clk_sccg_pll_wait_lock(pll);
 }

diff --git a/drivers/clk/nxp/clk-lpc18xx-ccu.c b/drivers/clk/nxp/clk-lpc18xx-ccu.c
index 27781b4..5969f62 100644 (file)
--- a/drivers/clk/nxp/clk-lpc18xx-ccu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-ccu.c
@@ -142,7 +142,7 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
         * Divider field is write only, so divider stat field must
         * be read so divider field can be set accordingly.
         */
-       val = clk_readl(gate->reg);
+       val = readl(gate->reg);
        if (val & LPC18XX_CCU_DIVSTAT)
                val |= LPC18XX_CCU_DIV;
 
@@ -155,12 +155,12 @@ static int lpc18xx_ccu_gate_endisable(struct clk_hw *hw, bool enable)
                 * and the next write should clear the RUN bit.
                 */
                val |= LPC18XX_CCU_AUTO;
-               clk_writel(val, gate->reg);
+               writel(val, gate->reg);
 
                val &= ~LPC18XX_CCU_RUN;
        }
 
-       clk_writel(val, gate->reg);
+       writel(val, gate->reg);
 
        return 0;
 }

diff --git a/drivers/clk/nxp/clk-lpc18xx-cgu.c b/drivers/clk/nxp/clk-lpc18xx-cgu.c
index 2531174..f5bc8bd 100644 (file)
--- a/drivers/clk/nxp/clk-lpc18xx-cgu.c
+++ b/drivers/clk/nxp/clk-lpc18xx-cgu.c
@@ -352,9 +352,9 @@ static unsigned long lpc18xx_pll0_recalc_rate(struct clk_hw *hw,
        struct lpc18xx_pll *pll = to_lpc_pll(hw);
        u32 ctrl, mdiv, msel, npdiv;
 
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
-       mdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
-       npdiv = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       mdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+       npdiv = readl(pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
 
        if (ctrl & LPC18XX_PLL0_CTRL_BYPASS)
                return parent_rate;
@@ -415,25 +415,25 @@ static int lpc18xx_pll0_set_rate(struct clk_hw *hw, unsigned long rate,
        m |= lpc18xx_pll0_msel2seli(m) << LPC18XX_PLL0_MDIV_SELI_SHIFT;
 
        /* Power down PLL, disable clk output and dividers */
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
        ctrl |= LPC18XX_PLL0_CTRL_PD;
        ctrl &= ~(LPC18XX_PLL0_CTRL_BYPASS | LPC18XX_PLL0_CTRL_DIRECTI |
                  LPC18XX_PLL0_CTRL_DIRECTO | LPC18XX_PLL0_CTRL_CLKEN);
-       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
 
        /* Configure new PLL settings */
-       clk_writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
-       clk_writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
+       writel(m, pll->reg + LPC18XX_CGU_PLL0USB_MDIV);
+       writel(LPC18XX_PLL0_NP_DIVS_1, pll->reg + LPC18XX_CGU_PLL0USB_NP_DIV);
 
        /* Power up PLL and wait for lock */
        ctrl &= ~LPC18XX_PLL0_CTRL_PD;
-       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
        do {
                udelay(10);
-               stat = clk_readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
+               stat = readl(pll->reg + LPC18XX_CGU_PLL0USB_STAT);
                if (stat & LPC18XX_PLL0_STAT_LOCK) {
                        ctrl |= LPC18XX_PLL0_CTRL_CLKEN;
-                       clk_writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
+                       writel(ctrl, pll->reg + LPC18XX_CGU_PLL0USB_CTRL);
 
                        return 0;
                }
@@ -458,8 +458,8 @@ static unsigned long lpc18xx_pll1_recalc_rate(struct clk_hw *hw,
        bool direct, fbsel;
        u32 stat, ctrl;
 
-       stat = clk_readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
-       ctrl = clk_readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
+       stat = readl(pll->reg + LPC18XX_CGU_PLL1_STAT);
+       ctrl = readl(pll->reg + LPC18XX_CGU_PLL1_CTRL);
 
        direct = (ctrl & LPC18XX_PLL1_CTRL_DIRECT) ? true : false;
        fbsel = (ctrl & LPC18XX_PLL1_CTRL_FBSEL) ? true : false;

diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 57c49fe..b0ded74 100644 (file)
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -119,7 +119,7 @@ static void __init r7s9210_update_clk_table(struct clk *extal_clk,
        if (clk_get_rate(extal_clk) > 12000000)
                cpg_mode = 1;
 
-       frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
+       frqcr = readl(base + CPG_FRQCR) & 0xFFF;
        if (frqcr == 0x012)
                index = 0;
        else if (frqcr == 0x112)

diff --git a/drivers/clk/rockchip/clk-ddr.c b/drivers/clk/rockchip/clk-ddr.c
index ebce526..09ede69 100644 (file)
--- a/drivers/clk/rockchip/clk-ddr.c
+++ b/drivers/clk/rockchip/clk-ddr.c
@@ -82,7 +82,7 @@ static u8 rockchip_ddrclk_get_parent(struct clk_hw *hw)
        struct rockchip_ddrclk *ddrclk = to_rockchip_ddrclk_hw(hw);
        u32 val;
 
-       val = clk_readl(ddrclk->reg_base +
+       val = readl(ddrclk->reg_base +
                        ddrclk->mux_offset) >> ddrclk->mux_shift;
        val &= GENMASK(ddrclk->mux_width - 1, 0);
 

diff --git a/drivers/clk/rockchip/clk-half-divider.c b/drivers/clk/rockchip/clk-half-divider.c
index b8da6e7..784b81e 100644 (file)
--- a/drivers/clk/rockchip/clk-half-divider.c
+++ b/drivers/clk/rockchip/clk-half-divider.c
@@ -24,7 +24,7 @@ static unsigned long clk_half_divider_recalc_rate(struct clk_hw *hw,
        struct clk_divider *divider = to_clk_divider(hw);
        unsigned int val;
 
-       val = clk_readl(divider->reg) >> divider->shift;
+       val = readl(divider->reg) >> divider->shift;
        val &= div_mask(divider->width);
        val = val * 2 + 3;
 
@@ -124,11 +124,11 @@ static int clk_half_divider_set_rate(struct clk_hw *hw, unsigned long rate,
        if (divider->flags & CLK_DIVIDER_HIWORD_MASK) {
                val = div_mask(divider->width) << (divider->shift + 16);
        } else {
-               val = clk_readl(divider->reg);
+               val = readl(divider->reg);
                val &= ~(div_mask(divider->width) << divider->shift);
        }
        val |= value << divider->shift;
-       clk_writel(val, divider->reg);
+       writel(val, divider->reg);
 
        if (divider->lock)
                spin_unlock_irqrestore(divider->lock, flags);

diff --git a/drivers/clk/tegra/clk-tegra124.c b/drivers/clk/tegra/clk-tegra124.c
index df0018f..abc0c4b 100644 (file)
--- a/drivers/clk/tegra/clk-tegra124.c
+++ b/drivers/clk/tegra/clk-tegra124.c
@@ -1466,9 +1466,9 @@ static void __init tegra124_132_clock_init_pre(struct device_node *np)
        tegra_pmc_clk_init(pmc_base, tegra124_clks);
 
        /* For Tegra124 & Tegra132, PLLD is the only source for DSIA & DSIB */
-       plld_base = clk_readl(clk_base + PLLD_BASE);
+       plld_base = readl(clk_base + PLLD_BASE);
        plld_base &= ~BIT(25);
-       clk_writel(plld_base, clk_base + PLLD_BASE);
+       writel(plld_base, clk_base + PLLD_BASE);
 }
 
 /**

diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c
index 7545af7..ed3c7df 100644 (file)
--- a/drivers/clk/tegra/clk-tegra210.c
+++ b/drivers/clk/tegra/clk-tegra210.c
@@ -3557,7 +3557,7 @@ static void __init tegra210_clock_init(struct device_node *np)
        if (!clks)
                return;
 
-       value = clk_readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
+       value = readl(clk_base + SPARE_REG0) >> CLK_M_DIVISOR_SHIFT;
        clk_m_div = (value & CLK_M_DIVISOR_MASK) + 1;
 
        if (tegra_osc_clk_init(clk_base, tegra210_clks, tegra210_input_freq,
@@ -3574,9 +3574,9 @@ static void __init tegra210_clock_init(struct device_node *np)
        tegra_pmc_clk_init(pmc_base, tegra210_clks);
 
        /* For Tegra210, PLLD is the only source for DSIA & DSIB */
-       value = clk_readl(clk_base + PLLD_BASE);
+       value = readl(clk_base + PLLD_BASE);
        value &= ~BIT(25);
-       clk_writel(value, clk_base + PLLD_BASE);
+       writel(value, clk_base + PLLD_BASE);
 
        tegra_clk_apply_init_table = tegra210_clock_apply_init_table;
 

diff --git a/drivers/clk/zynq/clkc.c b/drivers/clk/zynq/clkc.c
index d7b53ac..4b9d5c1 100644 (file)
--- a/drivers/clk/zynq/clkc.c
+++ b/drivers/clk/zynq/clkc.c
@@ -158,7 +158,7 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
        clks[fclk] = clk_register_gate(NULL, clk_name,
                        div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg,
                        0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock);
-       enable_reg = clk_readl(fclk_gate_reg) & 1;
+       enable_reg = readl(fclk_gate_reg) & 1;
        if (enable && !enable_reg) {
                if (clk_prepare_enable(clks[fclk]))
                        pr_warn("%s: FCLK%u enable failed\n", __func__,
@@ -287,7 +287,7 @@ static void __init zynq_clk_setup(struct device_node *np)
                        SLCR_IOPLL_CTRL, 4, 1, 0, &iopll_lock);
 
        /* CPU clocks */
-       tmp = clk_readl(SLCR_621_TRUE) & 1;
+       tmp = readl(SLCR_621_TRUE) & 1;
        clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
                        CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
                        &armclk_lock);
@@ -510,7 +510,7 @@ static void __init zynq_clk_setup(struct device_node *np)
                        &dbgclk_lock);
 
        /* leave debug clocks in the state the bootloader set them up to */
-       tmp = clk_readl(SLCR_DBG_CLK_CTRL);
+       tmp = readl(SLCR_DBG_CLK_CTRL);
        if (tmp & DBG_CLK_CTRL_CLKACT_TRC)
                if (clk_prepare_enable(clks[dbg_trc]))
                        pr_warn("%s: trace clk enable failed\n", __func__);

diff --git a/drivers/clk/zynq/pll.c b/drivers/clk/zynq/pll.c
index 00d72fb..800b70e 100644 (file)
--- a/drivers/clk/zynq/pll.c
+++ b/drivers/clk/zynq/pll.c
@@ -90,7 +90,7 @@ static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw,
         * makes probably sense to redundantly save fbdiv in the struct
         * zynq_pll to save the IO access.
         */
-       fbdiv = (clk_readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
+       fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >>
                        PLLCTRL_FBDIV_SHIFT;
 
        return parent_rate * fbdiv;
@@ -112,7 +112,7 @@ static int zynq_pll_is_enabled(struct clk_hw *hw)
 
        spin_lock_irqsave(clk->lock, flags);
 
-       reg = clk_readl(clk->pll_ctrl);
+       reg = readl(clk->pll_ctrl);
 
        spin_unlock_irqrestore(clk->lock, flags);
 
@@ -138,10 +138,10 @@ static int zynq_pll_enable(struct clk_hw *hw)
        /* Power up PLL and wait for lock */
        spin_lock_irqsave(clk->lock, flags);
 
-       reg = clk_readl(clk->pll_ctrl);
+       reg = readl(clk->pll_ctrl);
        reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK);
-       clk_writel(reg, clk->pll_ctrl);
-       while (!(clk_readl(clk->pll_status) & (1 << clk->lockbit)))
+       writel(reg, clk->pll_ctrl);
+       while (!(readl(clk->pll_status) & (1 << clk->lockbit)))
                ;
 
        spin_unlock_irqrestore(clk->lock, flags);
@@ -168,9 +168,9 @@ static void zynq_pll_disable(struct clk_hw *hw)
        /* shut down PLL */
        spin_lock_irqsave(clk->lock, flags);
 
-       reg = clk_readl(clk->pll_ctrl);
+       reg = readl(clk->pll_ctrl);
        reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK;
-       clk_writel(reg, clk->pll_ctrl);
+       writel(reg, clk->pll_ctrl);
 
        spin_unlock_irqrestore(clk->lock, flags);
 }
@@ -223,9 +223,9 @@ struct clk *clk_register_zynq_pll(const char *name, const char *parent,
 
        spin_lock_irqsave(pll->lock, flags);
 
-       reg = clk_readl(pll->pll_ctrl);
+       reg = readl(pll->pll_ctrl);
        reg &= ~PLLCTRL_BPQUAL_MASK;
-       clk_writel(reg, pll->pll_ctrl);
+       writel(reg, pll->pll_ctrl);
 
        spin_unlock_irqrestore(pll->lock, flags);
 

diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index c767a93..523318a 100644 (file)
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1013,21 +1013,6 @@ static inline int of_clk_detect_critical(struct device_node *np, int index,
 }
 #endif /* CONFIG_OF */
 
-/*
- * wrap access to peripherals in accessor routines
- * for improved portability across platforms
- */
-
-static inline u32 clk_readl(u32 __iomem *reg)
-{
-       return readl(reg);
-}
-
-static inline void clk_writel(u32 val, u32 __iomem *reg)
-{
-       writel(val, reg);
-}
-
 void clk_gate_restore_context(struct clk_hw *hw);
 
 #endif /* CONFIG_COMMON_CLK */