iommu/amd: Do not flush IRTE when only updating isRun and destination fields
authorSuravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Tue, 17 Oct 2023 14:42:36 +0000 (09:42 -0500)
committerJoerg Roedel <jroedel@suse.de>
Mon, 11 Dec 2023 14:21:35 +0000 (15:21 +0100)
According to the recent update in the AMD IOMMU spec [1], the IsRun and
Destination fields of the Interrupt Remapping Table Entry (IRTE) are not
cached by the IOMMU hardware.

Therefore, do not issue the INVALIDATE_INTERRUPT_TABLE command when
updating IRTE[IsRun] and IRTE[Destination] when IRTE[GuestMode]=1, which
should help improve IOMMU AVIC/x2AVIC performance.

References:
[1] AMD IOMMU Spec Revision (Rev 3.08-PUB)
Link: https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/specifications/48882_IOMMU.pdf)
Cc: Joao Martins <joao.m.martins@oracle.com>
Cc: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Reviewed-by: Vasant Hegde <vasant.hegde@amd.com>
Tested-by: Alejandro Jimenez <alejandro.j.jimenez@oracle.com>
Link: https://lore.kernel.org/r/20231017144236.8287-1-suravee.suthikulpanit@amd.com
Signed-off-by: Joerg Roedel <jroedel@suse.de>
drivers/iommu/amd/iommu.c

index 9f70643..b14046b 100644 (file)
@@ -3111,8 +3111,8 @@ out:
        return index;
 }
 
-static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
-                         struct irte_ga *irte)
+static int __modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
+                           struct irte_ga *irte)
 {
        struct irq_remap_table *table;
        struct irte_ga *entry;
@@ -3139,6 +3139,18 @@ static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
 
        raw_spin_unlock_irqrestore(&table->lock, flags);
 
+       return 0;
+}
+
+static int modify_irte_ga(struct amd_iommu *iommu, u16 devid, int index,
+                         struct irte_ga *irte)
+{
+       bool ret;
+
+       ret = __modify_irte_ga(iommu, devid, index, irte);
+       if (ret)
+               return ret;
+
        iommu_flush_irt_and_complete(iommu, devid);
 
        return 0;
@@ -3822,8 +3834,8 @@ int amd_iommu_update_ga(int cpu, bool is_run, void *data)
        }
        entry->lo.fields_vapic.is_run = is_run;
 
-       return modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
-                             ir_data->irq_2_irte.index, entry);
+       return __modify_irte_ga(ir_data->iommu, ir_data->irq_2_irte.devid,
+                               ir_data->irq_2_irte.index, entry);
 }
 EXPORT_SYMBOL(amd_iommu_update_ga);
 #endif