drm/xe/guc: Port Wa_14012197797/Wa_22011391025 to xe_wa
authorLucas De Marchi <lucas.demarchi@intel.com>
Fri, 26 May 2023 16:43:52 +0000 (09:43 -0700)
committerRodrigo Vivi <rodrigo.vivi@intel.com>
Tue, 19 Dec 2023 23:34:03 +0000 (18:34 -0500)
Wa_14012197797 and Wa_22011391025 apply to DG2 using the same action.
They apply to slightly different conditions. Add both to the oob rules
so they are both reported as active.

Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://lore.kernel.org/r/20230526164358.86393-16-lucas.demarchi@intel.com
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
drivers/gpu/drm/xe/xe_guc.c
drivers/gpu/drm/xe/xe_wa_oob.rules

index 1b3fbbd..54aaf6e 100644 (file)
@@ -147,14 +147,7 @@ static u32 guc_ctl_wa_flags(struct xe_guc *guc)
            xe->info.platform == XE_DG2)
                flags |= GUC_WA_HOLD_CCS_SWITCHOUT;
 
-       /*
-        * Wa_14012197797
-        * Wa_22011391025
-        *
-        * The same WA bit is used for both and 22011391025 is applicable to
-        * all DG2.
-        */
-       if (xe->info.platform == XE_DG2)
+       if (XE_WA(gt, 22011391025) || XE_WA(gt, 14012197797))
                flags |= GUC_WA_DUAL_QUEUE;
 
        /*
index 9b29a0d..77ac4a4 100644 (file)
@@ -1,2 +1,4 @@
 22012773006    GRAPHICS_VERSION_RANGE(1200, 1250)
 16011759253    SUBPLATFORM(DG2, G10), GRAPHICS_STEP(A0, B0)
+22011391025    PLATFORM(DG2)
+14012197797    PLATFORM(DG2), GRAPHICS_STEP(A0, B0)