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RDMA/hns: Fix initial arm_st of CQ
author
Haoyue Xu
<xuhaoyue1@hisilicon.com>
Fri, 29 Oct 2021 09:58:46 +0000
(17:58 +0800)
committer
Jason Gunthorpe
<jgg@nvidia.com>
Fri, 29 Oct 2021 14:51:34 +0000
(11:51 -0300)
We set the init CQ status to ARMED before. As a result, an unexpected CEQE
would be reported. Therefore, the init CQ status should be set to no_armed
rather than REG_NXT_CEQE.
Fixes:
a5073d6054f7
("RDMA/hns: Add eq support of hip08")
Link:
https://lore.kernel.org/r/20211029095846.26732-1-liangwenpeng@huawei.com
Signed-off-by: Haoyue Xu <xuhaoyue1@hisilicon.com>
Signed-off-by: Wenpeng Liang <liangwenpeng@huawei.com>
Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
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diff --git
a/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
b/drivers/infiniband/hw/hns/hns_roce_hw_v2.c
index
d5f3faa
..
8e5f086
100644
(file)
--- a/
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
+++ b/
drivers/infiniband/hw/hns/hns_roce_hw_v2.c
@@
-3328,7
+3328,7
@@
static void hns_roce_v2_write_cqc(struct hns_roce_dev *hr_dev,
memset(cq_context, 0, sizeof(*cq_context));
hr_reg_write(cq_context, CQC_CQ_ST, V2_CQ_STATE_VALID);
- hr_reg_write(cq_context, CQC_ARM_ST,
REG_NXT_CEQE
);
+ hr_reg_write(cq_context, CQC_ARM_ST,
NO_ARMED
);
hr_reg_write(cq_context, CQC_SHIFT, ilog2(hr_cq->cq_depth));
hr_reg_write(cq_context, CQC_CEQN, hr_cq->vector);
hr_reg_write(cq_context, CQC_CQN, hr_cq->cqn);