drm/i915/rkl: Don't try to access transcoder D

There are a couple places in our driver that loop over transcoders A..D
for gen11+; since RKL only has three pipes/transcoders, this can lead to
unclaimed register reads/writes.  We should add checks for transcoder
existence where appropriate.

v2: Move one transcoder check that wound up in the wrong function after
    conflict resolution.  It belongs in bdw_get_trans_port_sync_config
    rather than bxt_get_dsi_transcoder_state.

v3: Switch loops to use for_each_cpu_transcoder_masked() since this
    iterator already checks the platform's transcoder mask for us.
    (Ville)

Cc: Aditya Swarup <aditya.swarup@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200603211529.3005059-10-matthew.d.roper@intel.com
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4905746..8e823ba 100644 (file)
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2872,13 +2872,15 @@ static void gen11_display_irq_reset(struct drm_i915_private *dev_priv)
 {
        struct intel_uncore *uncore = &dev_priv->uncore;
        enum pipe pipe;
+       u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+               BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
 
        intel_uncore_write(uncore, GEN11_DISPLAY_INT_CTL, 0);
 
        if (INTEL_GEN(dev_priv) >= 12) {
                enum transcoder trans;
 
-               for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+               for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
                        enum intel_display_power_domain domain;
 
                        domain = POWER_DOMAIN_TRANSCODER(trans);
@@ -3400,6 +3402,8 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        u32 de_port_masked = gen8_de_port_aux_mask(dev_priv);
        u32 de_port_enables;
        u32 de_misc_masked = GEN8_DE_EDP_PSR;
+       u32 trans_mask = BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
+               BIT(TRANSCODER_C) | BIT(TRANSCODER_D);
        enum pipe pipe;
 
        if (INTEL_GEN(dev_priv) <= 10)
@@ -3420,7 +3424,7 @@ static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
        if (INTEL_GEN(dev_priv) >= 12) {
                enum transcoder trans;
 
-               for (trans = TRANSCODER_A; trans <= TRANSCODER_D; trans++) {
+               for_each_cpu_transcoder_masked(dev_priv, trans, trans_mask) {
                        enum intel_display_power_domain domain;
 
                        domain = POWER_DOMAIN_TRANSCODER(trans);