ARM: dts: imx53: Bind CPLD on M53Menlo

Enable ECSPI2 and bind CPLD to both chip selects.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/imx53-m53menlo.dts b/arch/arm/boot/dts/imx53-m53menlo.dts
index 55c122a..10acc53 100644 (file)
--- a/arch/arm/boot/dts/imx53-m53menlo.dts
+++ b/arch/arm/boot/dts/imx53-m53menlo.dts
@@ -100,6 +100,25 @@
        assigned-clock-rates = <133333334>, <33333334>, <33333334>;
 };
 
+&ecspi2 {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_ecspi2>;
+       cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>, <&gpio2 27 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+
+       spidev@0 {
+               compatible = "menlo,m53cpld";
+               spi-max-frequency = <25000000>;
+               reg = <0>;
+       };
+
+       spidev@1 {
+               compatible = "menlo,m53cpld";
+               spi-max-frequency = <25000000>;
+               reg = <1>;
+       };
+};
+
 &esdhc1 {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_esdhc1>;
@@ -301,6 +320,16 @@
                        >;
                };
 
+               pinctrl_ecspi2: ecspi2grp {
+                       fsl,pins = <
+                               MX53_PAD_EIM_CS0__ECSPI2_SCLK           0xe4
+                               MX53_PAD_EIM_OE__ECSPI2_MISO            0xe4
+                               MX53_PAD_EIM_CS1__ECSPI2_MOSI           0xe4
+                               MX53_PAD_EIM_RW__GPIO2_26               0xe4
+                               MX53_PAD_EIM_LBA__GPIO2_27              0xe4
+                       >;
+               };
+
                pinctrl_esdhc1: esdhc1grp {
                        fsl,pins = <
                                MX53_PAD_SD1_DATA0__ESDHC1_DAT0         0x1e4