drm/i915/display: Extract display workarounds from clock gating init

Several of the register updates that are currently done in the clock
gating init functions are actually display workarounds that should move
into the display-specific part of the code.  Furthermore, some of the
registers being programmed don't even have anything to do with clock
gating at all.

Extract the display workarounds for gen11 and later platforms to a
dedicated display/intel_display_wa.c file to keep these separate from
the SOC / sgunit clock gating that we need on some platforms.  The gen11
cutoff here is selected somewhat arbitrarily; this is the point where
workarounds were first assigned dedicated lineage numbers that can be
easily looked up and confirmed in the modern workaround database.  It
also avoids any confusion on older platforms where the exact boundaries
between display/GT/other IP blocks wasn't as well-defined as it is
today.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Lucas De Marchi <lucas.demarchi@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230907001009.3732474-2-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index 79f65ef..1b2e02e 100644 (file)
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -248,6 +248,7 @@ i915-y += \
        display/intel_display_power_well.o \
        display/intel_display_reset.o \
        display/intel_display_rps.o \
+       display/intel_display_wa.o \
        display/intel_dmc.o \
        display/intel_dpio_phy.o \
        display/intel_dpll.o \

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.c b/drivers/gpu/drm/i915/display/intel_display_wa.c
new file mode 100644 (file)
index 0000000..ac136fd
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.c
@@ -0,0 +1,48 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+#include "intel_de.h"
+#include "intel_display_wa.h"
+
+static void gen11_display_wa_apply(struct drm_i915_private *i915)
+{
+       /* Wa_1409120013 */
+       intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                      DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+
+       /* Wa_14010594013 */
+       intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, 0, ICL_DELAY_PMRSP);
+}
+
+static void xe_d_display_wa_apply(struct drm_i915_private *i915)
+{
+       /* Wa_1409120013 */
+       intel_de_write(i915, ILK_DPFC_CHICKEN(INTEL_FBC_A),
+                      DPFC_CHICKEN_COMP_DUMMY_PIXEL);
+
+       /* Wa_14013723622 */
+       intel_de_rmw(i915, CLKREQ_POLICY, CLKREQ_POLICY_MEM_UP_OVRD, 0);
+}
+
+static void adlp_display_wa_apply(struct drm_i915_private *i915)
+{
+       /* Wa_22011091694:adlp */
+       intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
+
+       /* Bspec/49189 Initialize Sequence */
+       intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
+}
+
+void intel_display_wa_apply(struct drm_i915_private *i915)
+{
+       if (IS_ALDERLAKE_P(i915))
+               adlp_display_wa_apply(i915);
+       else if (DISPLAY_VER(i915) == 12)
+               xe_d_display_wa_apply(i915);
+       else if (DISPLAY_VER(i915) == 11)
+               gen11_display_wa_apply(i915);
+}

diff --git a/drivers/gpu/drm/i915/display/intel_display_wa.h b/drivers/gpu/drm/i915/display/intel_display_wa.h
new file mode 100644 (file)
index 0000000..63201d0
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_wa.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_WA_H__
+#define __INTEL_DISPLAY_WA_H__
+
+struct drm_i915_private;
+
+void intel_display_wa_apply(struct drm_i915_private *i915);
+
+#endif

diff --git a/drivers/gpu/drm/i915/intel_clock_gating.c b/drivers/gpu/drm/i915/intel_clock_gating.c
index a58ac1b..7b0c1bc 100644 (file)
--- a/drivers/gpu/drm/i915/intel_clock_gating.c
+++ b/drivers/gpu/drm/i915/intel_clock_gating.c
@@ -28,6 +28,7 @@
 #include "display/intel_de.h"
 #include "display/intel_display.h"
 #include "display/intel_display_trace.h"
+#include "display/intel_display_wa.h"
 #include "display/skl_watermark.h"
 
 #include "gt/intel_engine_regs.h"
@@ -349,39 +350,6 @@ static void gen8_set_l3sqc_credits(struct drm_i915_private *i915,
        intel_uncore_write(&i915->uncore, GEN7_MISCCPCTL, misccpctl);
 }
 
-static void icl_init_clock_gating(struct drm_i915_private *i915)
-{
-       /* Wa_1409120013:icl,ehl */
-       intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
-                          DPFC_CHICKEN_COMP_DUMMY_PIXEL);
-
-       /*Wa_14010594013:icl, ehl */
-       intel_uncore_rmw(&i915->uncore, GEN8_CHICKEN_DCPR_1,
-                        0, ICL_DELAY_PMRSP);
-}
-
-static void gen12lp_init_clock_gating(struct drm_i915_private *i915)
-{
-       /* Wa_1409120013 */
-       if (DISPLAY_VER(i915) == 12)
-               intel_uncore_write(&i915->uncore, ILK_DPFC_CHICKEN(INTEL_FBC_A),
-                                  DPFC_CHICKEN_COMP_DUMMY_PIXEL);
-
-       /* Wa_14013723622:tgl,rkl,dg1,adl-s */
-       if (DISPLAY_VER(i915) == 12)
-               intel_uncore_rmw(&i915->uncore, CLKREQ_POLICY,
-                                CLKREQ_POLICY_MEM_UP_OVRD, 0);
-}
-
-static void adlp_init_clock_gating(struct drm_i915_private *i915)
-{
-       /* Wa_22011091694:adlp */
-       intel_de_rmw(i915, GEN9_CLKGATE_DIS_5, 0, DPCE_GATING_DIS);
-
-       /* Bspec/49189 Initialize Sequence */
-       intel_de_rmw(i915, GEN8_CHICKEN_DCPR_1, DDI_CLOCK_REG_ACCESS, 0);
-}
-
 static void xehpsdv_init_clock_gating(struct drm_i915_private *i915)
 {
        /* Wa_22010146351:xehpsdv */
@@ -790,6 +758,8 @@ static void i830_init_clock_gating(struct drm_i915_private *i915)
 void intel_clock_gating_init(struct drm_i915_private *i915)
 {
        i915->clock_gating_funcs->init_clock_gating(i915);
+
+       intel_display_wa_apply(i915);
 }
 
 static void nop_init_clock_gating(struct drm_i915_private *i915)
@@ -806,9 +776,6 @@ static const struct drm_i915_clock_gating_funcs platform##_clock_gating_funcs =
 CG_FUNCS(pvc);
 CG_FUNCS(dg2);
 CG_FUNCS(xehpsdv);
-CG_FUNCS(adlp);
-CG_FUNCS(gen12lp);
-CG_FUNCS(icl);
 CG_FUNCS(cfl);
 CG_FUNCS(skl);
 CG_FUNCS(kbl);
@@ -847,12 +814,6 @@ void intel_clock_gating_hooks_init(struct drm_i915_private *i915)
                i915->clock_gating_funcs = &dg2_clock_gating_funcs;
        else if (IS_XEHPSDV(i915))
                i915->clock_gating_funcs = &xehpsdv_clock_gating_funcs;
-       else if (IS_ALDERLAKE_P(i915))
-               i915->clock_gating_funcs = &adlp_clock_gating_funcs;
-       else if (DISPLAY_VER(i915) == 12)
-               i915->clock_gating_funcs = &gen12lp_clock_gating_funcs;
-       else if (GRAPHICS_VER(i915) == 11)
-               i915->clock_gating_funcs = &icl_clock_gating_funcs;
        else if (IS_COFFEELAKE(i915) || IS_COMETLAKE(i915))
                i915->clock_gating_funcs = &cfl_clock_gating_funcs;
        else if (IS_SKYLAKE(i915))