[ARM] 4508/1: S3C: Move items to include/asm-arm/plat-s3c

This patch moves items of the s3c24xx support into
a new plat-s3c directory for items that use the
s3c24xx support but are not directly s3c24xx
compatible, such as the s3c2400 and s3c6400.

git mv commands:
git mv include/asm-arm/arch-s3c2410/iic.h include/asm-arm/plat-s3c/iic.h
git mv include/asm-arm/arch-s3c2410/nand.h include/asm-arm/plat-s3c/nand.h
git mv include/asm-arm/arch-s3c2410/regs-iic.h include/asm-arm/plat-s3c/regs-iic.h
git mv include/asm-arm/arch-s3c2410/regs-nand.h include/asm-arm/plat-s3c/regs-nand.h
git mv include/asm-arm/arch-s3c2410/regs-rtc.h include/asm-arm/plat-s3c/regs-rtc.h
git mv include/asm-arm/arch-s3c2410/regs-serial.h include/asm-arm/plat-s3c/regs-serial.h
git mv include/asm-arm/arch-s3c2410/regs-timer.h include/asm-arm/plat-s3c/regs-timer.h
git mv include/asm-arm/arch-s3c2410/regs-watchdog.h include/asm-arm/plat-s3c/regs-watchdog.h

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

diff --git a/arch/arm/mach-s3c2410/clock.c b/arch/arm/mach-s3c2410/clock.c
index 5b4831c..cab9d62 100644 (file)
--- a/arch/arm/mach-s3c2410/clock.c
+++ b/arch/arm/mach-s3c2410/clock.c
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 

diff --git a/arch/arm/mach-s3c2410/dma.c b/arch/arm/mach-s3c2410/dma.c
index 67d1ad3..5620ca4 100644 (file)
--- a/arch/arm/mach-s3c2410/dma.c
+++ b/arch/arm/mach-s3c2410/dma.c
@@ -23,7 +23,7 @@
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/dma.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-ac97.h>
 #include <asm/arch/regs-mem.h>

diff --git a/arch/arm/mach-s3c2410/mach-amlm5900.c b/arch/arm/mach-s3c2410/mach-amlm5900.c
index 435adcc..43bb5e1 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-amlm5900.c
+++ b/arch/arm/mach-s3c2410/mach-amlm5900.c
@@ -48,7 +48,7 @@
 #include <asm/mach-types.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 

diff --git a/arch/arm/mach-s3c2410/mach-bast.c b/arch/arm/mach-s3c2410/mach-bast.c
index 8b52ea9..bc92699 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-bast.c
+++ b/arch/arm/mach-s3c2410/mach-bast.c
@@ -36,13 +36,13 @@
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
 
-#include <asm/arch/nand.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/nand.h>
+#include <asm/plat-s3c/iic.h>
 #include <asm/arch/fb.h>
 
 #include <linux/mtd/mtd.h>

diff --git a/arch/arm/mach-s3c2410/mach-h1940.c b/arch/arm/mach-s3c2410/mach-h1940.c
index 5c9bcea..4102235 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-h1940.c
+++ b/arch/arm/mach-s3c2410/mach-h1940.c
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-lcd.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>

diff --git a/arch/arm/mach-s3c2410/mach-n30.c b/arch/arm/mach-s3c2410/mach-n30.c
index 412e50c..621f548 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-n30.c
+++ b/arch/arm/mach-s3c2410/mach-n30.c
@@ -33,9 +33,9 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/iic.h>
+#include <asm/plat-s3c/iic.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/clock.h>

diff --git a/arch/arm/mach-s3c2410/mach-otom.c b/arch/arm/mach-s3c2410/mach-otom.c
index 1f899fa..717af40 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-otom.c
+++ b/arch/arm/mach-s3c2410/mach-otom.c
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>

diff --git a/arch/arm/mach-s3c2410/mach-qt2410.c b/arch/arm/mach-s3c2410/mach-qt2410.c
index d86e6f1..6cb4a0d 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-qt2410.c
+++ b/arch/arm/mach-s3c2410/mach-qt2410.c
@@ -49,9 +49,9 @@
 
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/fb.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 #include <asm/arch/udc.h>
 #include <asm/arch/spi.h>
 #include <asm/arch/spi-gpio.h>

diff --git a/arch/arm/mach-s3c2410/mach-smdk2410.c b/arch/arm/mach-s3c2410/mach-smdk2410.c
index 5852d30..2265505 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-smdk2410.c
+++ b/arch/arm/mach-s3c2410/mach-smdk2410.c
@@ -47,7 +47,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/devs.h>
 #include <asm/plat-s3c24xx/cpu.h>

diff --git a/arch/arm/mach-s3c2410/mach-vr1000.c b/arch/arm/mach-s3c2410/mach-vr1000.c
index 7b624bb..9f43f3f 100644 (file)
--- a/arch/arm/mach-s3c2410/mach-vr1000.c
+++ b/arch/arm/mach-s3c2410/mach-vr1000.c
@@ -39,7 +39,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 

diff --git a/arch/arm/mach-s3c2410/s3c2410.c b/arch/arm/mach-s3c2410/s3c2410.c
index 1a86a98..e580303 100644 (file)
--- a/arch/arm/mach-s3c2410/s3c2410.c
+++ b/arch/arm/mach-s3c2410/s3c2410.c
@@ -29,7 +29,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/cpu.h>
@@ -40,7 +40,6 @@
 
 static struct map_desc s3c2410_iodesc[] __initdata = {
        IODESC_ENT(CLKPWR),
-       IODESC_ENT(LCD),
        IODESC_ENT(TIMER),
        IODESC_ENT(WATCHDOG),
 };

diff --git a/arch/arm/mach-s3c2410/sleep.S b/arch/arm/mach-s3c2410/sleep.S
index d1eeed2..8a9c5a2 100644 (file)
--- a/arch/arm/mach-s3c2410/sleep.S
+++ b/arch/arm/mach-s3c2410/sleep.S
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
        /* s3c2410_cpu_suspend
         *

diff --git a/arch/arm/mach-s3c2412/clock.c b/arch/arm/mach-s3c2412/clock.c
index 6a8e444..8543dd6 100644 (file)
--- a/arch/arm/mach-s3c2412/clock.c
+++ b/arch/arm/mach-s3c2412/clock.c
@@ -37,7 +37,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 

diff --git a/arch/arm/mach-s3c2412/dma.c b/arch/arm/mach-s3c2412/dma.c
index 668ccce..48413df 100644 (file)
--- a/arch/arm/mach-s3c2412/dma.c
+++ b/arch/arm/mach-s3c2412/dma.c
@@ -24,7 +24,7 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-ac97.h>
 #include <asm/arch/regs-mem.h>

diff --git a/arch/arm/mach-s3c2412/mach-smdk2413.c b/arch/arm/mach-s3c2412/mach-smdk2413.c
index 063af09..bbc609c 100644 (file)
--- a/arch/arm/mach-s3c2412/mach-smdk2413.c
+++ b/arch/arm/mach-s3c2412/mach-smdk2413.c
@@ -32,7 +32,7 @@
 #include <asm/mach-types.h>
 
 //#include <asm/debug-ll.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 

diff --git a/arch/arm/mach-s3c2412/mach-vstms.c b/arch/arm/mach-s3c2412/mach-vstms.c
index f2fbd65..3298254 100644 (file)
--- a/arch/arm/mach-s3c2412/mach-vstms.c
+++ b/arch/arm/mach-s3c2412/mach-vstms.c
@@ -33,14 +33,14 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/idle.h>
 #include <asm/arch/fb.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2412.h>

diff --git a/arch/arm/mach-s3c2412/s3c2412.c b/arch/arm/mach-s3c2412/s3c2412.c
index 782b581..12995d8 100644 (file)
--- a/arch/arm/mach-s3c2412/s3c2412.c
+++ b/arch/arm/mach-s3c2412/s3c2412.c
@@ -34,7 +34,7 @@
 #include <asm/arch/idle.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-power.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>

diff --git a/arch/arm/mach-s3c2440/dma.c b/arch/arm/mach-s3c2440/dma.c
index cd035a3..13e4be3 100644 (file)
--- a/arch/arm/mach-s3c2440/dma.c
+++ b/arch/arm/mach-s3c2440/dma.c
@@ -23,7 +23,7 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-ac97.h>
 #include <asm/arch/regs-mem.h>

diff --git a/arch/arm/mach-s3c2440/mach-anubis.c b/arch/arm/mach-s3c2440/mach-anubis.c
index 29c163d..3d3dfa9 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-anubis.c
+++ b/arch/arm/mach-s3c2440/mach-anubis.c
@@ -34,11 +34,11 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>

diff --git a/arch/arm/mach-s3c2440/mach-nexcoder.c b/arch/arm/mach-s3c2440/mach-nexcoder.c
index 5e61f21..afe0d7b 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-nexcoder.c
+++ b/arch/arm/mach-s3c2440/mach-nexcoder.c
@@ -36,7 +36,7 @@
 
 //#include <asm/debug-ll.h>
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/s3c2410.h>
 #include <asm/plat-s3c24xx/s3c2440.h>

diff --git a/arch/arm/mach-s3c2440/mach-osiris.c b/arch/arm/mach-s3c2440/mach-osiris.c
index 89f4c9c..0ba7e90 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-osiris.c
+++ b/arch/arm/mach-s3c2440/mach-osiris.c
@@ -31,11 +31,11 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>
 #include <asm/arch/regs-lcd.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <linux/mtd/mtd.h>
 #include <linux/mtd/nand.h>

diff --git a/arch/arm/mach-s3c2440/mach-rx3715.c b/arch/arm/mach-s3c2440/mach-rx3715.c
index 866ff71..b59e6d3 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-rx3715.c
+++ b/arch/arm/mach-s3c2440/mach-rx3715.c
@@ -38,12 +38,12 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 
 #include <asm/arch/h1940.h>
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 #include <asm/arch/fb.h>
 
 #include <asm/plat-s3c24xx/clock.h>

diff --git a/arch/arm/mach-s3c2440/mach-smdk2440.c b/arch/arm/mach-s3c2440/mach-smdk2440.c
index e167254..670115b 100644 (file)
--- a/arch/arm/mach-s3c2440/mach-smdk2440.c
+++ b/arch/arm/mach-s3c2440/mach-smdk2440.c
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 

diff --git a/arch/arm/mach-s3c2443/dma.c b/arch/arm/mach-s3c2443/dma.c
index f70e8cc..d8bb434 100644 (file)
--- a/arch/arm/mach-s3c2443/dma.c
+++ b/arch/arm/mach-s3c2443/dma.c
@@ -24,7 +24,7 @@
 #include <asm/plat-s3c24xx/dma.h>
 #include <asm/plat-s3c24xx/cpu.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-ac97.h>
 #include <asm/arch/regs-mem.h>

diff --git a/arch/arm/mach-s3c2443/mach-smdk2443.c b/arch/arm/mach-s3c2443/mach-smdk2443.c
index b1eb709..8cd9313 100644 (file)
--- a/arch/arm/mach-s3c2443/mach-smdk2443.c
+++ b/arch/arm/mach-s3c2443/mach-smdk2443.c
@@ -31,7 +31,7 @@
 #include <asm/irq.h>
 #include <asm/mach-types.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-lcd.h>
 

diff --git a/arch/arm/plat-s3c24xx/common-smdk.c b/arch/arm/plat-s3c24xx/common-smdk.c
index 7ed19b2..398c7ac 100644 (file)
--- a/arch/arm/plat-s3c24xx/common-smdk.c
+++ b/arch/arm/plat-s3c24xx/common-smdk.c
@@ -38,7 +38,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/leds-gpio.h>
 
-#include <asm/arch/nand.h>
+#include <asm/plat-s3c/nand.h>
 
 #include <asm/plat-s3c24xx/common-smdk.h>
 #include <asm/plat-s3c24xx/devs.h>

diff --git a/arch/arm/plat-s3c24xx/cpu.c b/arch/arm/plat-s3c24xx/cpu.c
index 8ce4904..f513ab0 100644 (file)
--- a/arch/arm/plat-s3c24xx/cpu.c
+++ b/arch/arm/plat-s3c24xx/cpu.c
@@ -38,7 +38,7 @@
 #include <asm/mach/map.h>
 
 #include <asm/arch/regs-gpio.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 #include <asm/plat-s3c24xx/cpu.h>
 #include <asm/plat-s3c24xx/devs.h>

diff --git a/arch/arm/plat-s3c24xx/devs.c b/arch/arm/plat-s3c24xx/devs.c
index 5875da0..9941508 100644 (file)
--- a/arch/arm/plat-s3c24xx/devs.c
+++ b/arch/arm/plat-s3c24xx/devs.c
@@ -28,7 +28,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/udc.h>
 
 #include <asm/plat-s3c24xx/devs.h>

diff --git a/arch/arm/plat-s3c24xx/pm.c b/arch/arm/plat-s3c24xx/pm.c
index 5692ecc..eab1850 100644 (file)
--- a/arch/arm/plat-s3c24xx/pm.c
+++ b/arch/arm/plat-s3c24xx/pm.c
@@ -40,7 +40,7 @@
 #include <asm/hardware.h>
 #include <asm/io.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-mem.h>

diff --git a/arch/arm/plat-s3c24xx/s3c244x.c b/arch/arm/plat-s3c24xx/s3c244x.c
index 767f2e9..8b2d47f 100644 (file)
--- a/arch/arm/plat-s3c24xx/s3c244x.c
+++ b/arch/arm/plat-s3c24xx/s3c244x.c
@@ -30,7 +30,7 @@
 #include <asm/irq.h>
 
 #include <asm/arch/regs-clock.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-gpioj.h>
 #include <asm/arch/regs-dsc.h>

diff --git a/arch/arm/plat-s3c24xx/sleep.S b/arch/arm/plat-s3c24xx/sleep.S
index 7b7ae79..d47113b 100644 (file)
--- a/arch/arm/plat-s3c24xx/sleep.S
+++ b/arch/arm/plat-s3c24xx/sleep.S
@@ -32,7 +32,7 @@
 #include <asm/arch/regs-gpio.h>
 #include <asm/arch/regs-clock.h>
 #include <asm/arch/regs-mem.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 
 /* CONFIG_DEBUG_RESUME is dangerous if your bootloader does not
  * reset the UART configuration, only enable if you really need this!

diff --git a/arch/arm/plat-s3c24xx/time.c b/arch/arm/plat-s3c24xx/time.c
index b766737..2ec1daa 100644 (file)
--- a/arch/arm/plat-s3c24xx/time.c
+++ b/arch/arm/plat-s3c24xx/time.c
@@ -33,7 +33,7 @@
 #include <asm/io.h>
 #include <asm/irq.h>
 #include <asm/arch/map.h>
-#include <asm/arch/regs-timer.h>
+#include <asm/plat-s3c/regs-timer.h>
 #include <asm/arch/regs-irq.h>
 #include <asm/mach/time.h>
 

diff --git a/drivers/serial/s3c2410.c b/drivers/serial/s3c2410.c
index 10bc020..3f26c4b 100644 (file)
--- a/drivers/serial/s3c2410.c
+++ b/drivers/serial/s3c2410.c
@@ -78,7 +78,7 @@
 
 #include <asm/hardware.h>
 
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 /* structures */

diff --git a/include/asm-arm/arch-s3c2410/debug-macro.S b/include/asm-arm/arch-s3c2410/debug-macro.S
index 9306486..90dfba4 100644 (file)
--- a/include/asm-arm/arch-s3c2410/debug-macro.S
+++ b/include/asm-arm/arch-s3c2410/debug-macro.S
@@ -13,7 +13,7 @@
 */
 
 #include <asm/arch/map.h>
-#include <asm/arch/regs-serial.h>
+#include <asm/plat-s3c/regs-serial.h>
 #include <asm/arch/regs-gpio.h>
 
 #define S3C2410_UART1_OFF (0x4000)

diff --git a/include/asm-arm/arch-s3c2410/iic.h b/include/asm-arm/arch-s3c2410/iic.h
deleted file mode 100644 (file)
index 71211c8..0000000
--- a/include/asm-arm/arch-s3c2410/iic.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/iic.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - I2C Controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_ARCH_IIC_H
-#define __ASM_ARCH_IIC_H __FILE__
-
-#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
-
-/* Notes:
- *     1) All frequencies are expressed in Hz
- *     2) A value of zero is `do not care`
-*/
-
-struct s3c2410_platform_i2c {
-       unsigned int    flags;
-       unsigned int    slave_addr;     /* slave address for controller */
-       unsigned long   bus_freq;       /* standard bus frequency */
-       unsigned long   max_freq;       /* max frequency for the bus */
-       unsigned long   min_freq;       /* min frequency for the bus */
-       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
-};
-
-#endif /* __ASM_ARCH_IIC_H */

diff --git a/include/asm-arm/arch-s3c2410/nand.h b/include/asm-arm/arch-s3c2410/nand.h
deleted file mode 100644 (file)
index 8816f7f..0000000
--- a/include/asm-arm/arch-s3c2410/nand.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/nand.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *     Ben Dooks <ben@simtec.co.uk>
- *
- * S3C2410 - NAND device controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* struct s3c2410_nand_set
- *
- * define an set of one or more nand chips registered with an unique mtd
- *
- * nr_chips     = number of chips in this set
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * name                 = name of set (optional)
- * nr_map       = map for low-layer logical to physical chip numbers (option)
- * partitions   = mtd partition list
-*/
-
-struct s3c2410_nand_set {
-       int                     nr_chips;
-       int                     nr_partitions;
-       char                    *name;
-       int                     *nr_map;
-       struct mtd_partition    *partitions;
-};
-
-struct s3c2410_platform_nand {
-       /* timing information for controller, all times in nanoseconds */
-
-       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
-       int     twrph0; /* active time for nWE/nOE */
-       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
-
-       int                     nr_sets;
-       struct s3c2410_nand_set *sets;
-
-       void                    (*select_chip)(struct s3c2410_nand_set *,
-                                              int chip);
-};
-

diff --git a/include/asm-arm/arch-s3c2410/regs-iic.h b/include/asm-arm/arch-s3c2410/regs-iic.h
deleted file mode 100644 (file)
index 2ae2952..0000000
--- a/include/asm-arm/arch-s3c2410/regs-iic.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
- *
- * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
- *             http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 I2C Controller
-*/
-
-#ifndef __ASM_ARCH_REGS_IIC_H
-#define __ASM_ARCH_REGS_IIC_H __FILE__
-
-/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
-
-#define S3C2410_IICREG(x) (x)
-
-#define S3C2410_IICCON    S3C2410_IICREG(0x00)
-#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
-#define S3C2410_IICADD    S3C2410_IICREG(0x08)
-#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
-#define S3C2440_IICLC    S3C2410_IICREG(0x10)
-
-#define S3C2410_IICCON_ACKEN           (1<<7)
-#define S3C2410_IICCON_TXDIV_16                (0<<6)
-#define S3C2410_IICCON_TXDIV_512       (1<<6)
-#define S3C2410_IICCON_IRQEN           (1<<5)
-#define S3C2410_IICCON_IRQPEND         (1<<4)
-#define S3C2410_IICCON_SCALE(x)                ((x)&15)
-#define S3C2410_IICCON_SCALEMASK       (0xf)
-
-#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
-#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
-#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
-#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
-#define S3C2410_IICSTAT_MODEMASK       (3<<6)
-
-#define S3C2410_IICSTAT_START          (1<<5)
-#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
-#define S3C2410_IICSTAT_TXRXEN         (1<<4)
-#define S3C2410_IICSTAT_ARBITR         (1<<3)
-#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
-#define S3C2410_IICSTAT_ADDR0          (1<<1)
-#define S3C2410_IICSTAT_LASTBIT                (1<<0)
-
-#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
-#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
-#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
-#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
-#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
-
-#define S3C2410_IICLC_FILTER_ON                (1<<2)
-
-#endif /* __ASM_ARCH_REGS_IIC_H */

diff --git a/include/asm-arm/arch-s3c2410/regs-nand.h b/include/asm-arm/arch-s3c2410/regs-nand.h
deleted file mode 100644 (file)
index b824d37..0000000
--- a/include/asm-arm/arch-s3c2410/regs-nand.h
+++ /dev/null
@@ -1,123 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
- *
- * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
- *                   http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 NAND register definitions
-*/
-
-#ifndef __ASM_ARM_REGS_NAND
-#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
-
-
-#define S3C2410_NFREG(x) (x)
-
-#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
-#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
-#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
-#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
-#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
-#define S3C2410_NFECC   S3C2410_NFREG(0x14)
-
-#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
-#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
-#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
-#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
-#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
-#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
-#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
-#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
-#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
-#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
-#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
-#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
-#define S3C2440_NFSECC   S3C24E10_NFREG(0x34)
-#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
-#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
-
-#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
-#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
-#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
-#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
-#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
-#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
-#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
-#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
-
-#define S3C2410_NFCONF_EN          (1<<15)
-#define S3C2410_NFCONF_512BYTE     (1<<14)
-#define S3C2410_NFCONF_4STEP       (1<<13)
-#define S3C2410_NFCONF_INITECC     (1<<12)
-#define S3C2410_NFCONF_nFCE        (1<<11)
-#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
-#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
-#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
-
-#define S3C2410_NFSTAT_BUSY        (1<<0)
-
-#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
-#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
-#define S3C2440_NFCONF_ADVFLASH                (1<<3)
-#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
-#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
-#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
-
-#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
-#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
-#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
-#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
-#define S3C2440_NFCONT_RN_FALLING      (1<<8)
-#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
-#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
-#define S3C2440_NFCONT_INITECC         (1<<4)
-#define S3C2440_NFCONT_nFCE            (1<<1)
-#define S3C2440_NFCONT_ENABLE          (1<<0)
-
-#define S3C2440_NFSTAT_READY           (1<<0)
-#define S3C2440_NFSTAT_nCE             (1<<1)
-#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
-#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
-
-#define S3C2412_NFCONF_NANDBOOT                (1<<31)
-#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
-#define S3C2412_NFCONF_ECC_MLC         (1<<24)
-#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
-
-#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
-#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
-#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
-#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
-#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
-#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
-#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
-#define S3C2412_NFCONT_nFCE1           (1<<2)
-#define S3C2412_NFCONT_nFCE0           (1<<1)
-
-#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
-#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
-#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
-#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
-#define S3C2412_NFSTAT_nFCE1           (1<<3)
-#define S3C2412_NFSTAT_nFCE0           (1<<2)
-#define S3C2412_NFSTAT_Res1            (1<<1)
-#define S3C2412_NFSTAT_READY           (1<<0)
-
-#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
-#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
-#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
-#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
-#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
-#define S3C2412_NFECCERR_NONE          (0)
-#define S3C2412_NFECCERR_1BIT          (1)
-#define S3C2412_NFECCERR_MULTIBIT      (2)
-#define S3C2412_NFECCERR_ECCAREA       (3)
-
-
-
-#endif /* __ASM_ARM_REGS_NAND */
-

diff --git a/include/asm-arm/arch-s3c2410/regs-rtc.h b/include/asm-arm/arch-s3c2410/regs-rtc.h
deleted file mode 100644 (file)
index 93b03c4..0000000
--- a/include/asm-arm/arch-s3c2410/regs-rtc.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-rtc.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                   http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Internal RTC register definition
-*/
-
-#ifndef __ASM_ARCH_REGS_RTC_H
-#define __ASM_ARCH_REGS_RTC_H __FILE__
-
-#define S3C2410_RTCREG(x) (x)
-
-#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
-#define S3C2410_RTCCON_RTCEN  (1<<0)
-#define S3C2410_RTCCON_CLKSEL (1<<1)
-#define S3C2410_RTCCON_CNTSEL (1<<2)
-#define S3C2410_RTCCON_CLKRST (1<<3)
-
-#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
-#define S3C2410_TICNT_ENABLE  (1<<7)
-
-#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
-#define S3C2410_RTCALM_ALMEN  (1<<6)
-#define S3C2410_RTCALM_YEAREN (1<<5)
-#define S3C2410_RTCALM_MONEN  (1<<4)
-#define S3C2410_RTCALM_DAYEN  (1<<3)
-#define S3C2410_RTCALM_HOUREN (1<<2)
-#define S3C2410_RTCALM_MINEN  (1<<1)
-#define S3C2410_RTCALM_SECEN  (1<<0)
-
-#define S3C2410_RTCALM_ALL \
-  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
-  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
-  S3C2410_RTCALM_SECEN
-
-
-#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
-#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
-#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
-
-#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
-#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
-#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
-
-#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
-
-#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
-#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
-#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
-#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
-#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
-#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
-#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
-
-
-#endif /* __ASM_ARCH_REGS_RTC_H */

diff --git a/include/asm-arm/arch-s3c2410/regs-serial.h b/include/asm-arm/arch-s3c2410/regs-serial.h
deleted file mode 100644 (file)
index 8946702..0000000
--- a/include/asm-arm/arch-s3c2410/regs-serial.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
- *
- *  From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- *  Adapted from:
- *
- *  Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-
-#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
-#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )
-
-#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
-
-#define S3C2410_URXH     (0x24)
-#define S3C2410_UTXH     (0x20)
-#define S3C2410_ULCON    (0x00)
-#define S3C2410_UCON     (0x04)
-#define S3C2410_UFCON    (0x08)
-#define S3C2410_UMCON    (0x0C)
-#define S3C2410_UBRDIV   (0x28)
-#define S3C2410_UTRSTAT          (0x10)
-#define S3C2410_UERSTAT          (0x14)
-#define S3C2410_UFSTAT   (0x18)
-#define S3C2410_UMSTAT   (0x1C)
-
-#define S3C2410_LCON_CFGMASK     ((0xF<<3)|(0x3))
-
-#define S3C2410_LCON_CS5         (0x0)
-#define S3C2410_LCON_CS6         (0x1)
-#define S3C2410_LCON_CS7         (0x2)
-#define S3C2410_LCON_CS8         (0x3)
-#define S3C2410_LCON_CSMASK      (0x3)
-
-#define S3C2410_LCON_PNONE       (0x0)
-#define S3C2410_LCON_PEVEN       (0x5 << 3)
-#define S3C2410_LCON_PODD        (0x4 << 3)
-#define S3C2410_LCON_PMASK       (0x7 << 3)
-
-#define S3C2410_LCON_STOPB       (1<<2)
-#define S3C2410_LCON_IRM          (1<<6)
-
-#define S3C2440_UCON_CLKMASK     (3<<10)
-#define S3C2440_UCON_PCLK        (0<<10)
-#define S3C2440_UCON_UCLK        (1<<10)
-#define S3C2440_UCON_PCLK2       (2<<10)
-#define S3C2440_UCON_FCLK        (3<<10)
-#define S3C2443_UCON_EPLL        (3<<10)
-
-#define S3C2440_UCON2_FCLK_EN    (1<<15)
-#define S3C2440_UCON0_DIVMASK    (15 << 12)
-#define S3C2440_UCON1_DIVMASK    (15 << 12)
-#define S3C2440_UCON2_DIVMASK    (7 << 12)
-#define S3C2440_UCON_DIVSHIFT    (12)
-
-#define S3C2412_UCON_CLKMASK   (3<<10)
-#define S3C2412_UCON_UCLK      (1<<10)
-#define S3C2412_UCON_USYSCLK   (3<<10)
-#define S3C2412_UCON_PCLK      (0<<10)
-#define S3C2412_UCON_PCLK2     (2<<10)
-
-#define S3C2410_UCON_UCLK        (1<<10)
-#define S3C2410_UCON_SBREAK      (1<<4)
-
-#define S3C2410_UCON_TXILEVEL    (1<<9)
-#define S3C2410_UCON_RXILEVEL    (1<<8)
-#define S3C2410_UCON_TXIRQMODE   (1<<2)
-#define S3C2410_UCON_RXIRQMODE   (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI          (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
-#define S3C2443_UCON_LOOPBACK    (1<<5)
-
-#define S3C2410_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL  | \
-                                  S3C2410_UCON_RXILEVEL  | \
-                                  S3C2410_UCON_TXIRQMODE | \
-                                  S3C2410_UCON_RXIRQMODE | \
-                                  S3C2410_UCON_RXFIFO_TOI)
-
-#define S3C2410_UFCON_FIFOMODE   (1<<0)
-#define S3C2410_UFCON_TXTRIG0    (0<<6)
-#define S3C2410_UFCON_RXTRIG8    (1<<4)
-#define S3C2410_UFCON_RXTRIG12   (2<<4)
-
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1    (0<<4)
-#define S3C2440_UFCON_RXTRIG8    (1<<4)
-#define S3C2440_UFCON_RXTRIG16   (2<<4)
-#define S3C2440_UFCON_RXTRIG32   (3<<4)
-
-#define S3C2440_UFCON_TXTRIG0    (0<<6)
-#define S3C2440_UFCON_TXTRIG16   (1<<6)
-#define S3C2440_UFCON_TXTRIG32   (2<<6)
-#define S3C2440_UFCON_TXTRIG48   (3<<6)
-
-#define S3C2410_UFCON_RESETBOTH          (3<<1)
-#define S3C2410_UFCON_RESETTX    (1<<2)
-#define S3C2410_UFCON_RESETRX    (1<<1)
-
-#define S3C2410_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE | \
-                                  S3C2410_UFCON_TXTRIG0  | \
-                                  S3C2410_UFCON_RXTRIG8 )
-
-#define        S3C2410_UMCOM_AFC         (1<<4)
-#define        S3C2410_UMCOM_RTS_LOW     (1<<0)
-
-#define S3C2412_UMCON_AFC_63   (0<<5)          /* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56   (1<<5)
-#define S3C2412_UMCON_AFC_48   (2<<5)
-#define S3C2412_UMCON_AFC_40   (3<<5)
-#define S3C2412_UMCON_AFC_32   (4<<5)
-#define S3C2412_UMCON_AFC_24   (5<<5)
-#define S3C2412_UMCON_AFC_16   (6<<5)
-#define S3C2412_UMCON_AFC_8    (7<<5)
-
-#define S3C2410_UFSTAT_TXFULL    (1<<9)
-#define S3C2410_UFSTAT_RXFULL    (1<<8)
-#define S3C2410_UFSTAT_TXMASK    (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT   (4)
-#define S3C2410_UFSTAT_RXMASK    (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT   (0)
-
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL    (1<<14)
-#define S3C2440_UFSTAT_RXFULL    (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT   (8)
-#define S3C2440_UFSTAT_RXSHIFT   (0)
-#define S3C2440_UFSTAT_TXMASK    (63<<8)
-#define S3C2440_UFSTAT_RXMASK    (63)
-
-#define S3C2410_UTRSTAT_TXE      (1<<2)
-#define S3C2410_UTRSTAT_TXFE     (1<<1)
-#define S3C2410_UTRSTAT_RXDR     (1<<0)
-
-#define S3C2410_UERSTAT_OVERRUN          (1<<0)
-#define S3C2410_UERSTAT_FRAME    (1<<2)
-#define S3C2410_UERSTAT_BREAK    (1<<3)
-#define S3C2443_UERSTAT_PARITY   (1<<1)
-
-#define S3C2410_UERSTAT_ANY      (S3C2410_UERSTAT_OVERRUN | \
-                                  S3C2410_UERSTAT_FRAME | \
-                                  S3C2410_UERSTAT_BREAK)
-
-#define S3C2410_UMSTAT_CTS       (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS          (1<<2)
-
-#define S3C2443_DIVSLOT                  (0x2C)
-
-#ifndef __ASSEMBLY__
-
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
-       const char      *name;
-       unsigned int     divisor;
-       unsigned int     min_baud;
-       unsigned int     max_baud;
-};
-
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-
-struct s3c2410_uartcfg {
-       unsigned char      hwport;       /* hardware port number */
-       unsigned char      unused;
-       unsigned short     flags;
-       upf_t              uart_flags;   /* default uart flags */
-
-       unsigned long      ucon;         /* value of ucon for port */
-       unsigned long      ulcon;        /* value of ulcon for port */
-       unsigned long      ufcon;        /* value of ufcon for port */
-
-       struct s3c24xx_uart_clksrc *clocks;
-       unsigned int                clocks_size;
-};
-
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-
-extern struct platform_device *s3c24xx_uart_devs[3];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARM_REGS_SERIAL_H */
-

diff --git a/include/asm-arm/arch-s3c2410/regs-timer.h b/include/asm-arm/arch-s3c2410/regs-timer.h
deleted file mode 100644 (file)
index 6f8fe43..0000000
--- a/include/asm-arm/arch-s3c2410/regs-timer.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-timer.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                   http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Timer configuration
-*/
-
-
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
-
-#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
-#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-
-#define S3C2410_TCFG0        S3C2410_TIMERREG(0x00)
-#define S3C2410_TCFG1        S3C2410_TIMERREG(0x04)
-#define S3C2410_TCON         S3C2410_TIMERREG(0x08)
-
-#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
-#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
-#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
-#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
-#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX4_DIV2          (0<<16)
-#define S3C2410_TCFG1_MUX4_DIV4          (1<<16)
-#define S3C2410_TCFG1_MUX4_DIV8          (2<<16)
-#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
-#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
-#define S3C2410_TCFG1_MUX4_MASK          (15<<16)
-#define S3C2410_TCFG1_MUX4_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX3_DIV2          (0<<12)
-#define S3C2410_TCFG1_MUX3_DIV4          (1<<12)
-#define S3C2410_TCFG1_MUX3_DIV8          (2<<12)
-#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
-#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
-#define S3C2410_TCFG1_MUX3_MASK          (15<<12)
-
-
-#define S3C2410_TCFG1_MUX2_DIV2          (0<<8)
-#define S3C2410_TCFG1_MUX2_DIV4          (1<<8)
-#define S3C2410_TCFG1_MUX2_DIV8          (2<<8)
-#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
-#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
-#define S3C2410_TCFG1_MUX2_MASK          (15<<8)
-
-
-#define S3C2410_TCFG1_MUX1_DIV2          (0<<4)
-#define S3C2410_TCFG1_MUX1_DIV4          (1<<4)
-#define S3C2410_TCFG1_MUX1_DIV8          (2<<4)
-#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
-#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
-#define S3C2410_TCFG1_MUX1_MASK          (15<<4)
-
-#define S3C2410_TCFG1_MUX0_DIV2          (0<<0)
-#define S3C2410_TCFG1_MUX0_DIV4          (1<<0)
-#define S3C2410_TCFG1_MUX0_DIV8          (2<<0)
-#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
-#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
-#define S3C2410_TCFG1_MUX0_MASK          (15<<0)
-
-/* for each timer, we have an count buffer, an compare buffer and
- * an observation buffer
-*/
-
-/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-
-#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
-
-#define S3C2410_TCON_T4RELOAD    (1<<22)
-#define S3C2410_TCON_T4MANUALUPD  (1<<21)
-#define S3C2410_TCON_T4START     (1<<20)
-
-#define S3C2410_TCON_T3RELOAD    (1<<19)
-#define S3C2410_TCON_T3INVERT    (1<<18)
-#define S3C2410_TCON_T3MANUALUPD  (1<<17)
-#define S3C2410_TCON_T3START     (1<<16)
-
-#define S3C2410_TCON_T2RELOAD    (1<<15)
-#define S3C2410_TCON_T2INVERT    (1<<14)
-#define S3C2410_TCON_T2MANUALUPD  (1<<13)
-#define S3C2410_TCON_T2START     (1<<12)
-
-#define S3C2410_TCON_T1RELOAD    (1<<11)
-#define S3C2410_TCON_T1INVERT    (1<<10)
-#define S3C2410_TCON_T1MANUALUPD  (1<<9)
-#define S3C2410_TCON_T1START     (1<<8)
-
-#define S3C2410_TCON_T0DEADZONE          (1<<4)
-#define S3C2410_TCON_T0RELOAD    (1<<3)
-#define S3C2410_TCON_T0INVERT    (1<<2)
-#define S3C2410_TCON_T0MANUALUPD  (1<<1)
-#define S3C2410_TCON_T0START     (1<<0)
-
-#endif /*  __ASM_ARCH_REGS_TIMER_H */
-
-
-

diff --git a/include/asm-arm/arch-s3c2410/regs-watchdog.h b/include/asm-arm/arch-s3c2410/regs-watchdog.h
deleted file mode 100644 (file)
index a9c5d49..0000000
--- a/include/asm-arm/arch-s3c2410/regs-watchdog.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                   http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Watchdog timer control
-*/
-
-
-#ifndef __ASM_ARCH_REGS_WATCHDOG_H
-#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
-
-#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
-
-#define S3C2410_WTCON     S3C2410_WDOGREG(0x00)
-#define S3C2410_WTDAT     S3C2410_WDOGREG(0x04)
-#define S3C2410_WTCNT     S3C2410_WDOGREG(0x08)
-
-/* the watchdog can either generate a reset pulse, or an
- * interrupt.
- */
-
-#define S3C2410_WTCON_RSTEN   (0x01)
-#define S3C2410_WTCON_INTEN   (1<<2)
-#define S3C2410_WTCON_ENABLE  (1<<5)
-
-#define S3C2410_WTCON_DIV16   (0<<3)
-#define S3C2410_WTCON_DIV32   (1<<3)
-#define S3C2410_WTCON_DIV64   (2<<3)
-#define S3C2410_WTCON_DIV128  (3<<3)
-
-#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
-#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
-
-#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
-
-

diff --git a/include/asm-arm/arch-s3c2410/system.h b/include/asm-arm/arch-s3c2410/system.h
index 1c74ef1..6389178 100644 (file)
--- a/include/asm-arm/arch-s3c2410/system.h
+++ b/include/asm-arm/arch-s3c2410/system.h
@@ -17,7 +17,7 @@
 #include <asm/arch/idle.h>
 #include <asm/arch/reset.h>
 
-#include <asm/arch/regs-watchdog.h>
+#include <asm/plat-s3c/regs-watchdog.h>
 #include <asm/arch/regs-clock.h>
 
 void (*s3c24xx_idle)(void);

diff --git a/include/asm-arm/arch-s3c2410/uncompress.h b/include/asm-arm/arch-s3c2410/uncompress.h
index dcb2cef..295c89c 100644 (file)
--- a/include/asm-arm/arch-s3c2410/uncompress.h
+++ b/include/asm-arm/arch-s3c2410/uncompress.h
@@ -16,9 +16,9 @@
 typedef unsigned int upf_t;    /* cannot include linux/serial_core.h */
 
 /* defines for UART registers */
-#include "asm/arch/regs-serial.h"
+#include "asm/plat-s3c/regs-serial.h"
 #include "asm/arch/regs-gpio.h"
-#include "asm/arch/regs-watchdog.h"
+#include "asm/plat-s3c/regs-watchdog.h"
 
 #include <asm/arch/map.h>
 

diff --git a/include/asm-arm/plat-s3c/iic.h b/include/asm-arm/plat-s3c/iic.h
new file mode 100644 (file)
index 0000000..71211c8
--- /dev/null
+++ b/include/asm-arm/plat-s3c/iic.h
@@ -0,0 +1,32 @@
+/* linux/include/asm-arm/arch-s3c2410/iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - I2C Controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+#ifndef __ASM_ARCH_IIC_H
+#define __ASM_ARCH_IIC_H __FILE__
+
+#define S3C_IICFLG_FILTER      (1<<0)  /* enable s3c2440 filter */
+
+/* Notes:
+ *     1) All frequencies are expressed in Hz
+ *     2) A value of zero is `do not care`
+*/
+
+struct s3c2410_platform_i2c {
+       unsigned int    flags;
+       unsigned int    slave_addr;     /* slave address for controller */
+       unsigned long   bus_freq;       /* standard bus frequency */
+       unsigned long   max_freq;       /* max frequency for the bus */
+       unsigned long   min_freq;       /* min frequency for the bus */
+       unsigned int    sda_delay;      /* pclks (s3c2440 only) */
+};
+
+#endif /* __ASM_ARCH_IIC_H */

diff --git a/include/asm-arm/plat-s3c/nand.h b/include/asm-arm/plat-s3c/nand.h
new file mode 100644 (file)
index 0000000..8816f7f
--- /dev/null
+++ b/include/asm-arm/plat-s3c/nand.h
@@ -0,0 +1,45 @@
+/* linux/include/asm-arm/arch-s3c2410/nand.h
+ *
+ * Copyright (c) 2004 Simtec Electronics
+ *     Ben Dooks <ben@simtec.co.uk>
+ *
+ * S3C2410 - NAND device controller platfrom_device info
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+*/
+
+/* struct s3c2410_nand_set
+ *
+ * define an set of one or more nand chips registered with an unique mtd
+ *
+ * nr_chips     = number of chips in this set
+ * nr_partitions = number of partitions pointed to be partitoons (or zero)
+ * name                 = name of set (optional)
+ * nr_map       = map for low-layer logical to physical chip numbers (option)
+ * partitions   = mtd partition list
+*/
+
+struct s3c2410_nand_set {
+       int                     nr_chips;
+       int                     nr_partitions;
+       char                    *name;
+       int                     *nr_map;
+       struct mtd_partition    *partitions;
+};
+
+struct s3c2410_platform_nand {
+       /* timing information for controller, all times in nanoseconds */
+
+       int     tacls;  /* time for active CLE/ALE to nWE/nOE */
+       int     twrph0; /* active time for nWE/nOE */
+       int     twrph1; /* time for release CLE/ALE from nWE/nOE inactive */
+
+       int                     nr_sets;
+       struct s3c2410_nand_set *sets;
+
+       void                    (*select_chip)(struct s3c2410_nand_set *,
+                                              int chip);
+};
+

diff --git a/include/asm-arm/plat-s3c/regs-iic.h b/include/asm-arm/plat-s3c/regs-iic.h
new file mode 100644 (file)
index 0000000..2ae2952
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-iic.h
@@ -0,0 +1,56 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-iic.h
+ *
+ * Copyright (c) 2004 Simtec Electronics <linux@simtec.co.uk>
+ *             http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 I2C Controller
+*/
+
+#ifndef __ASM_ARCH_REGS_IIC_H
+#define __ASM_ARCH_REGS_IIC_H __FILE__
+
+/* see s3c2410x user guide, v1.1, section 9 (p447) for more info */
+
+#define S3C2410_IICREG(x) (x)
+
+#define S3C2410_IICCON    S3C2410_IICREG(0x00)
+#define S3C2410_IICSTAT   S3C2410_IICREG(0x04)
+#define S3C2410_IICADD    S3C2410_IICREG(0x08)
+#define S3C2410_IICDS     S3C2410_IICREG(0x0C)
+#define S3C2440_IICLC    S3C2410_IICREG(0x10)
+
+#define S3C2410_IICCON_ACKEN           (1<<7)
+#define S3C2410_IICCON_TXDIV_16                (0<<6)
+#define S3C2410_IICCON_TXDIV_512       (1<<6)
+#define S3C2410_IICCON_IRQEN           (1<<5)
+#define S3C2410_IICCON_IRQPEND         (1<<4)
+#define S3C2410_IICCON_SCALE(x)                ((x)&15)
+#define S3C2410_IICCON_SCALEMASK       (0xf)
+
+#define S3C2410_IICSTAT_MASTER_RX      (2<<6)
+#define S3C2410_IICSTAT_MASTER_TX      (3<<6)
+#define S3C2410_IICSTAT_SLAVE_RX       (0<<6)
+#define S3C2410_IICSTAT_SLAVE_TX       (1<<6)
+#define S3C2410_IICSTAT_MODEMASK       (3<<6)
+
+#define S3C2410_IICSTAT_START          (1<<5)
+#define S3C2410_IICSTAT_BUSBUSY                (1<<5)
+#define S3C2410_IICSTAT_TXRXEN         (1<<4)
+#define S3C2410_IICSTAT_ARBITR         (1<<3)
+#define S3C2410_IICSTAT_ASSLAVE                (1<<2)
+#define S3C2410_IICSTAT_ADDR0          (1<<1)
+#define S3C2410_IICSTAT_LASTBIT                (1<<0)
+
+#define S3C2410_IICLC_SDA_DELAY0       (0 << 0)
+#define S3C2410_IICLC_SDA_DELAY5       (1 << 0)
+#define S3C2410_IICLC_SDA_DELAY10      (2 << 0)
+#define S3C2410_IICLC_SDA_DELAY15      (3 << 0)
+#define S3C2410_IICLC_SDA_DELAY_MASK   (3 << 0)
+
+#define S3C2410_IICLC_FILTER_ON                (1<<2)
+
+#endif /* __ASM_ARCH_REGS_IIC_H */

diff --git a/include/asm-arm/plat-s3c/regs-nand.h b/include/asm-arm/plat-s3c/regs-nand.h
new file mode 100644 (file)
index 0000000..b824d37
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-nand.h
@@ -0,0 +1,123 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-nand.h
+ *
+ * Copyright (c) 2004,2005 Simtec Electronics <linux@simtec.co.uk>
+ *                   http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 NAND register definitions
+*/
+
+#ifndef __ASM_ARM_REGS_NAND
+#define __ASM_ARM_REGS_NAND "$Id: nand.h,v 1.3 2003/12/09 11:36:29 ben Exp $"
+
+
+#define S3C2410_NFREG(x) (x)
+
+#define S3C2410_NFCONF  S3C2410_NFREG(0x00)
+#define S3C2410_NFCMD   S3C2410_NFREG(0x04)
+#define S3C2410_NFADDR  S3C2410_NFREG(0x08)
+#define S3C2410_NFDATA  S3C2410_NFREG(0x0C)
+#define S3C2410_NFSTAT  S3C2410_NFREG(0x10)
+#define S3C2410_NFECC   S3C2410_NFREG(0x14)
+
+#define S3C2440_NFCONT   S3C2410_NFREG(0x04)
+#define S3C2440_NFCMD    S3C2410_NFREG(0x08)
+#define S3C2440_NFADDR   S3C2410_NFREG(0x0C)
+#define S3C2440_NFDATA   S3C2410_NFREG(0x10)
+#define S3C2440_NFECCD0  S3C2410_NFREG(0x14)
+#define S3C2440_NFECCD1  S3C2410_NFREG(0x18)
+#define S3C2440_NFECCD   S3C2410_NFREG(0x1C)
+#define S3C2440_NFSTAT   S3C2410_NFREG(0x20)
+#define S3C2440_NFESTAT0 S3C2410_NFREG(0x24)
+#define S3C2440_NFESTAT1 S3C2410_NFREG(0x28)
+#define S3C2440_NFMECC0  S3C2410_NFREG(0x2C)
+#define S3C2440_NFMECC1  S3C2410_NFREG(0x30)
+#define S3C2440_NFSECC   S3C24E10_NFREG(0x34)
+#define S3C2440_NFSBLK   S3C2410_NFREG(0x38)
+#define S3C2440_NFEBLK   S3C2410_NFREG(0x3C)
+
+#define S3C2412_NFSBLK         S3C2410_NFREG(0x20)
+#define S3C2412_NFEBLK         S3C2410_NFREG(0x24)
+#define S3C2412_NFSTAT         S3C2410_NFREG(0x28)
+#define S3C2412_NFMECC_ERR0    S3C2410_NFREG(0x2C)
+#define S3C2412_NFMECC_ERR1    S3C2410_NFREG(0x30)
+#define S3C2412_NFMECC0                S3C2410_NFREG(0x34)
+#define S3C2412_NFMECC1                S3C2410_NFREG(0x38)
+#define S3C2412_NFSECC         S3C2410_NFREG(0x3C)
+
+#define S3C2410_NFCONF_EN          (1<<15)
+#define S3C2410_NFCONF_512BYTE     (1<<14)
+#define S3C2410_NFCONF_4STEP       (1<<13)
+#define S3C2410_NFCONF_INITECC     (1<<12)
+#define S3C2410_NFCONF_nFCE        (1<<11)
+#define S3C2410_NFCONF_TACLS(x)    ((x)<<8)
+#define S3C2410_NFCONF_TWRPH0(x)   ((x)<<4)
+#define S3C2410_NFCONF_TWRPH1(x)   ((x)<<0)
+
+#define S3C2410_NFSTAT_BUSY        (1<<0)
+
+#define S3C2440_NFCONF_BUSWIDTH_8      (0<<0)
+#define S3C2440_NFCONF_BUSWIDTH_16     (1<<0)
+#define S3C2440_NFCONF_ADVFLASH                (1<<3)
+#define S3C2440_NFCONF_TACLS(x)                ((x)<<12)
+#define S3C2440_NFCONF_TWRPH0(x)       ((x)<<8)
+#define S3C2440_NFCONF_TWRPH1(x)       ((x)<<4)
+
+#define S3C2440_NFCONT_LOCKTIGHT       (1<<13)
+#define S3C2440_NFCONT_SOFTLOCK                (1<<12)
+#define S3C2440_NFCONT_ILLEGALACC_EN   (1<<10)
+#define S3C2440_NFCONT_RNBINT_EN       (1<<9)
+#define S3C2440_NFCONT_RN_FALLING      (1<<8)
+#define S3C2440_NFCONT_SPARE_ECCLOCK   (1<<6)
+#define S3C2440_NFCONT_MAIN_ECCLOCK    (1<<5)
+#define S3C2440_NFCONT_INITECC         (1<<4)
+#define S3C2440_NFCONT_nFCE            (1<<1)
+#define S3C2440_NFCONT_ENABLE          (1<<0)
+
+#define S3C2440_NFSTAT_READY           (1<<0)
+#define S3C2440_NFSTAT_nCE             (1<<1)
+#define S3C2440_NFSTAT_RnB_CHANGE      (1<<2)
+#define S3C2440_NFSTAT_ILLEGAL_ACCESS  (1<<3)
+
+#define S3C2412_NFCONF_NANDBOOT                (1<<31)
+#define S3C2412_NFCONF_ECCCLKCON       (1<<30)
+#define S3C2412_NFCONF_ECC_MLC         (1<<24)
+#define S3C2412_NFCONF_TACLS_MASK      (7<<12) /* 1 extra bit of Tacls */
+
+#define S3C2412_NFCONT_ECC4_DIRWR      (1<<18)
+#define S3C2412_NFCONT_LOCKTIGHT       (1<<17)
+#define S3C2412_NFCONT_SOFTLOCK                (1<<16)
+#define S3C2412_NFCONT_ECC4_ENCINT     (1<<13)
+#define S3C2412_NFCONT_ECC4_DECINT     (1<<12)
+#define S3C2412_NFCONT_MAIN_ECC_LOCK   (1<<7)
+#define S3C2412_NFCONT_INIT_MAIN_ECC   (1<<5)
+#define S3C2412_NFCONT_nFCE1           (1<<2)
+#define S3C2412_NFCONT_nFCE0           (1<<1)
+
+#define S3C2412_NFSTAT_ECC_ENCDONE     (1<<7)
+#define S3C2412_NFSTAT_ECC_DECDONE     (1<<6)
+#define S3C2412_NFSTAT_ILLEGAL_ACCESS  (1<<5)
+#define S3C2412_NFSTAT_RnB_CHANGE      (1<<4)
+#define S3C2412_NFSTAT_nFCE1           (1<<3)
+#define S3C2412_NFSTAT_nFCE0           (1<<2)
+#define S3C2412_NFSTAT_Res1            (1<<1)
+#define S3C2412_NFSTAT_READY           (1<<0)
+
+#define S3C2412_NFECCERR_SERRDATA(x)   (((x) >> 21) & 0xf)
+#define S3C2412_NFECCERR_SERRBIT(x)    (((x) >> 18) & 0x7)
+#define S3C2412_NFECCERR_MERRDATA(x)   (((x) >> 7) & 0x3ff)
+#define S3C2412_NFECCERR_MERRBIT(x)    (((x) >> 4) & 0x7)
+#define S3C2412_NFECCERR_SPARE_ERR(x)  (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_MAIN_ERR(x)   (((x) >> 2) & 0x3)
+#define S3C2412_NFECCERR_NONE          (0)
+#define S3C2412_NFECCERR_1BIT          (1)
+#define S3C2412_NFECCERR_MULTIBIT      (2)
+#define S3C2412_NFECCERR_ECCAREA       (3)
+
+
+
+#endif /* __ASM_ARM_REGS_NAND */
+

diff --git a/include/asm-arm/plat-s3c/regs-rtc.h b/include/asm-arm/plat-s3c/regs-rtc.h
new file mode 100644 (file)
index 0000000..93b03c4
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-rtc.h
@@ -0,0 +1,61 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-rtc.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                   http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Internal RTC register definition
+*/
+
+#ifndef __ASM_ARCH_REGS_RTC_H
+#define __ASM_ARCH_REGS_RTC_H __FILE__
+
+#define S3C2410_RTCREG(x) (x)
+
+#define S3C2410_RTCCON       S3C2410_RTCREG(0x40)
+#define S3C2410_RTCCON_RTCEN  (1<<0)
+#define S3C2410_RTCCON_CLKSEL (1<<1)
+#define S3C2410_RTCCON_CNTSEL (1<<2)
+#define S3C2410_RTCCON_CLKRST (1<<3)
+
+#define S3C2410_TICNT        S3C2410_RTCREG(0x44)
+#define S3C2410_TICNT_ENABLE  (1<<7)
+
+#define S3C2410_RTCALM       S3C2410_RTCREG(0x50)
+#define S3C2410_RTCALM_ALMEN  (1<<6)
+#define S3C2410_RTCALM_YEAREN (1<<5)
+#define S3C2410_RTCALM_MONEN  (1<<4)
+#define S3C2410_RTCALM_DAYEN  (1<<3)
+#define S3C2410_RTCALM_HOUREN (1<<2)
+#define S3C2410_RTCALM_MINEN  (1<<1)
+#define S3C2410_RTCALM_SECEN  (1<<0)
+
+#define S3C2410_RTCALM_ALL \
+  S3C2410_RTCALM_ALMEN | S3C2410_RTCALM_YEAREN | S3C2410_RTCALM_MONEN |\
+  S3C2410_RTCALM_DAYEN | S3C2410_RTCALM_HOUREN | S3C2410_RTCALM_MINEN |\
+  S3C2410_RTCALM_SECEN
+
+
+#define S3C2410_ALMSEC       S3C2410_RTCREG(0x54)
+#define S3C2410_ALMMIN       S3C2410_RTCREG(0x58)
+#define S3C2410_ALMHOUR              S3C2410_RTCREG(0x5c)
+
+#define S3C2410_ALMDATE              S3C2410_RTCREG(0x60)
+#define S3C2410_ALMMON       S3C2410_RTCREG(0x64)
+#define S3C2410_ALMYEAR              S3C2410_RTCREG(0x68)
+
+#define S3C2410_RTCRST       S3C2410_RTCREG(0x6c)
+
+#define S3C2410_RTCSEC       S3C2410_RTCREG(0x70)
+#define S3C2410_RTCMIN       S3C2410_RTCREG(0x74)
+#define S3C2410_RTCHOUR              S3C2410_RTCREG(0x78)
+#define S3C2410_RTCDATE              S3C2410_RTCREG(0x7c)
+#define S3C2410_RTCDAY       S3C2410_RTCREG(0x80)
+#define S3C2410_RTCMON       S3C2410_RTCREG(0x84)
+#define S3C2410_RTCYEAR              S3C2410_RTCREG(0x88)
+
+
+#endif /* __ASM_ARCH_REGS_RTC_H */

diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
new file mode 100644 (file)
index 0000000..8946702
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-serial.h
@@ -0,0 +1,232 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-serial.h
+ *
+ *  From linux/include/asm-arm/hardware/serial_s3c2410.h
+ *
+ *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
+ *
+ *  Adapted from:
+ *
+ *  Internal header file for MX1ADS serial ports (UART1 & 2)
+ *
+ *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
+*/
+
+#ifndef __ASM_ARM_REGS_SERIAL_H
+#define __ASM_ARM_REGS_SERIAL_H
+
+#define S3C24XX_VA_UART0      (S3C24XX_VA_UART)
+#define S3C24XX_VA_UART1      (S3C24XX_VA_UART + 0x4000 )
+#define S3C24XX_VA_UART2      (S3C24XX_VA_UART + 0x8000 )
+#define S3C24XX_VA_UART3      (S3C24XX_VA_UART + 0xC000 )
+
+#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
+#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
+#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
+#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
+
+#define S3C2410_URXH     (0x24)
+#define S3C2410_UTXH     (0x20)
+#define S3C2410_ULCON    (0x00)
+#define S3C2410_UCON     (0x04)
+#define S3C2410_UFCON    (0x08)
+#define S3C2410_UMCON    (0x0C)
+#define S3C2410_UBRDIV   (0x28)
+#define S3C2410_UTRSTAT          (0x10)
+#define S3C2410_UERSTAT          (0x14)
+#define S3C2410_UFSTAT   (0x18)
+#define S3C2410_UMSTAT   (0x1C)
+
+#define S3C2410_LCON_CFGMASK     ((0xF<<3)|(0x3))
+
+#define S3C2410_LCON_CS5         (0x0)
+#define S3C2410_LCON_CS6         (0x1)
+#define S3C2410_LCON_CS7         (0x2)
+#define S3C2410_LCON_CS8         (0x3)
+#define S3C2410_LCON_CSMASK      (0x3)
+
+#define S3C2410_LCON_PNONE       (0x0)
+#define S3C2410_LCON_PEVEN       (0x5 << 3)
+#define S3C2410_LCON_PODD        (0x4 << 3)
+#define S3C2410_LCON_PMASK       (0x7 << 3)
+
+#define S3C2410_LCON_STOPB       (1<<2)
+#define S3C2410_LCON_IRM          (1<<6)
+
+#define S3C2440_UCON_CLKMASK     (3<<10)
+#define S3C2440_UCON_PCLK        (0<<10)
+#define S3C2440_UCON_UCLK        (1<<10)
+#define S3C2440_UCON_PCLK2       (2<<10)
+#define S3C2440_UCON_FCLK        (3<<10)
+#define S3C2443_UCON_EPLL        (3<<10)
+
+#define S3C2440_UCON2_FCLK_EN    (1<<15)
+#define S3C2440_UCON0_DIVMASK    (15 << 12)
+#define S3C2440_UCON1_DIVMASK    (15 << 12)
+#define S3C2440_UCON2_DIVMASK    (7 << 12)
+#define S3C2440_UCON_DIVSHIFT    (12)
+
+#define S3C2412_UCON_CLKMASK   (3<<10)
+#define S3C2412_UCON_UCLK      (1<<10)
+#define S3C2412_UCON_USYSCLK   (3<<10)
+#define S3C2412_UCON_PCLK      (0<<10)
+#define S3C2412_UCON_PCLK2     (2<<10)
+
+#define S3C2410_UCON_UCLK        (1<<10)
+#define S3C2410_UCON_SBREAK      (1<<4)
+
+#define S3C2410_UCON_TXILEVEL    (1<<9)
+#define S3C2410_UCON_RXILEVEL    (1<<8)
+#define S3C2410_UCON_TXIRQMODE   (1<<2)
+#define S3C2410_UCON_RXIRQMODE   (1<<0)
+#define S3C2410_UCON_RXFIFO_TOI          (1<<7)
+#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
+#define S3C2443_UCON_LOOPBACK    (1<<5)
+
+#define S3C2410_UCON_DEFAULT     (S3C2410_UCON_TXILEVEL  | \
+                                  S3C2410_UCON_RXILEVEL  | \
+                                  S3C2410_UCON_TXIRQMODE | \
+                                  S3C2410_UCON_RXIRQMODE | \
+                                  S3C2410_UCON_RXFIFO_TOI)
+
+#define S3C2410_UFCON_FIFOMODE   (1<<0)
+#define S3C2410_UFCON_TXTRIG0    (0<<6)
+#define S3C2410_UFCON_RXTRIG8    (1<<4)
+#define S3C2410_UFCON_RXTRIG12   (2<<4)
+
+/* S3C2440 FIFO trigger levels */
+#define S3C2440_UFCON_RXTRIG1    (0<<4)
+#define S3C2440_UFCON_RXTRIG8    (1<<4)
+#define S3C2440_UFCON_RXTRIG16   (2<<4)
+#define S3C2440_UFCON_RXTRIG32   (3<<4)
+
+#define S3C2440_UFCON_TXTRIG0    (0<<6)
+#define S3C2440_UFCON_TXTRIG16   (1<<6)
+#define S3C2440_UFCON_TXTRIG32   (2<<6)
+#define S3C2440_UFCON_TXTRIG48   (3<<6)
+
+#define S3C2410_UFCON_RESETBOTH          (3<<1)
+#define S3C2410_UFCON_RESETTX    (1<<2)
+#define S3C2410_UFCON_RESETRX    (1<<1)
+
+#define S3C2410_UFCON_DEFAULT    (S3C2410_UFCON_FIFOMODE | \
+                                  S3C2410_UFCON_TXTRIG0  | \
+                                  S3C2410_UFCON_RXTRIG8 )
+
+#define        S3C2410_UMCOM_AFC         (1<<4)
+#define        S3C2410_UMCOM_RTS_LOW     (1<<0)
+
+#define S3C2412_UMCON_AFC_63   (0<<5)          /* same as s3c2443 */
+#define S3C2412_UMCON_AFC_56   (1<<5)
+#define S3C2412_UMCON_AFC_48   (2<<5)
+#define S3C2412_UMCON_AFC_40   (3<<5)
+#define S3C2412_UMCON_AFC_32   (4<<5)
+#define S3C2412_UMCON_AFC_24   (5<<5)
+#define S3C2412_UMCON_AFC_16   (6<<5)
+#define S3C2412_UMCON_AFC_8    (7<<5)
+
+#define S3C2410_UFSTAT_TXFULL    (1<<9)
+#define S3C2410_UFSTAT_RXFULL    (1<<8)
+#define S3C2410_UFSTAT_TXMASK    (15<<4)
+#define S3C2410_UFSTAT_TXSHIFT   (4)
+#define S3C2410_UFSTAT_RXMASK    (15<<0)
+#define S3C2410_UFSTAT_RXSHIFT   (0)
+
+/* UFSTAT S3C2443 same as S3C2440 */
+#define S3C2440_UFSTAT_TXFULL    (1<<14)
+#define S3C2440_UFSTAT_RXFULL    (1<<6)
+#define S3C2440_UFSTAT_TXSHIFT   (8)
+#define S3C2440_UFSTAT_RXSHIFT   (0)
+#define S3C2440_UFSTAT_TXMASK    (63<<8)
+#define S3C2440_UFSTAT_RXMASK    (63)
+
+#define S3C2410_UTRSTAT_TXE      (1<<2)
+#define S3C2410_UTRSTAT_TXFE     (1<<1)
+#define S3C2410_UTRSTAT_RXDR     (1<<0)
+
+#define S3C2410_UERSTAT_OVERRUN          (1<<0)
+#define S3C2410_UERSTAT_FRAME    (1<<2)
+#define S3C2410_UERSTAT_BREAK    (1<<3)
+#define S3C2443_UERSTAT_PARITY   (1<<1)
+
+#define S3C2410_UERSTAT_ANY      (S3C2410_UERSTAT_OVERRUN | \
+                                  S3C2410_UERSTAT_FRAME | \
+                                  S3C2410_UERSTAT_BREAK)
+
+#define S3C2410_UMSTAT_CTS       (1<<0)
+#define S3C2410_UMSTAT_DeltaCTS          (1<<2)
+
+#define S3C2443_DIVSLOT                  (0x2C)
+
+#ifndef __ASSEMBLY__
+
+/* struct s3c24xx_uart_clksrc
+ *
+ * this structure defines a named clock source that can be used for the
+ * uart, so that the best clock can be selected for the requested baud
+ * rate.
+ *
+ * min_baud and max_baud define the range of baud-rates this clock is
+ * acceptable for, if they are both zero, it is assumed any baud rate that
+ * can be generated from this clock will be used.
+ *
+ * divisor gives the divisor from the clock to the one seen by the uart
+*/
+
+struct s3c24xx_uart_clksrc {
+       const char      *name;
+       unsigned int     divisor;
+       unsigned int     min_baud;
+       unsigned int     max_baud;
+};
+
+/* configuration structure for per-machine configurations for the
+ * serial port
+ *
+ * the pointer is setup by the machine specific initialisation from the
+ * arch/arm/mach-s3c2410/ directory.
+*/
+
+struct s3c2410_uartcfg {
+       unsigned char      hwport;       /* hardware port number */
+       unsigned char      unused;
+       unsigned short     flags;
+       upf_t              uart_flags;   /* default uart flags */
+
+       unsigned long      ucon;         /* value of ucon for port */
+       unsigned long      ulcon;        /* value of ulcon for port */
+       unsigned long      ufcon;        /* value of ufcon for port */
+
+       struct s3c24xx_uart_clksrc *clocks;
+       unsigned int                clocks_size;
+};
+
+/* s3c24xx_uart_devs
+ *
+ * this is exported from the core as we cannot use driver_register(),
+ * or platform_add_device() before the console_initcall()
+*/
+
+extern struct platform_device *s3c24xx_uart_devs[3];
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_ARM_REGS_SERIAL_H */
+

diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
new file mode 100644 (file)
index 0000000..6f8fe43
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-timer.h
@@ -0,0 +1,106 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-timer.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                   http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Timer configuration
+*/
+
+
+#ifndef __ASM_ARCH_REGS_TIMER_H
+#define __ASM_ARCH_REGS_TIMER_H "$Id: timer.h,v 1.4 2003/05/06 19:30:50 ben Exp $"
+
+#define S3C2410_TIMERREG(x) (S3C24XX_VA_TIMER + (x))
+#define S3C2410_TIMERREG2(tmr,reg) S3C2410_TIMERREG((reg)+0x0c+((tmr)*0x0c))
+
+#define S3C2410_TCFG0        S3C2410_TIMERREG(0x00)
+#define S3C2410_TCFG1        S3C2410_TIMERREG(0x04)
+#define S3C2410_TCON         S3C2410_TIMERREG(0x08)
+
+#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
+#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
+#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
+#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
+#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX4_DIV2          (0<<16)
+#define S3C2410_TCFG1_MUX4_DIV4          (1<<16)
+#define S3C2410_TCFG1_MUX4_DIV8          (2<<16)
+#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
+#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
+#define S3C2410_TCFG1_MUX4_MASK          (15<<16)
+#define S3C2410_TCFG1_MUX4_SHIFT  (16)
+
+#define S3C2410_TCFG1_MUX3_DIV2          (0<<12)
+#define S3C2410_TCFG1_MUX3_DIV4          (1<<12)
+#define S3C2410_TCFG1_MUX3_DIV8          (2<<12)
+#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
+#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
+#define S3C2410_TCFG1_MUX3_MASK          (15<<12)
+
+
+#define S3C2410_TCFG1_MUX2_DIV2          (0<<8)
+#define S3C2410_TCFG1_MUX2_DIV4          (1<<8)
+#define S3C2410_TCFG1_MUX2_DIV8          (2<<8)
+#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
+#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
+#define S3C2410_TCFG1_MUX2_MASK          (15<<8)
+
+
+#define S3C2410_TCFG1_MUX1_DIV2          (0<<4)
+#define S3C2410_TCFG1_MUX1_DIV4          (1<<4)
+#define S3C2410_TCFG1_MUX1_DIV8          (2<<4)
+#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
+#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
+#define S3C2410_TCFG1_MUX1_MASK          (15<<4)
+
+#define S3C2410_TCFG1_MUX0_DIV2          (0<<0)
+#define S3C2410_TCFG1_MUX0_DIV4          (1<<0)
+#define S3C2410_TCFG1_MUX0_DIV8          (2<<0)
+#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
+#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
+#define S3C2410_TCFG1_MUX0_MASK          (15<<0)
+
+/* for each timer, we have an count buffer, an compare buffer and
+ * an observation buffer
+*/
+
+/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
+
+#define S3C2410_TCNTB(tmr)    S3C2410_TIMERREG2(tmr, 0x00)
+#define S3C2410_TCMPB(tmr)    S3C2410_TIMERREG2(tmr, 0x04)
+#define S3C2410_TCNTO(tmr)    S3C2410_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
+
+#define S3C2410_TCON_T4RELOAD    (1<<22)
+#define S3C2410_TCON_T4MANUALUPD  (1<<21)
+#define S3C2410_TCON_T4START     (1<<20)
+
+#define S3C2410_TCON_T3RELOAD    (1<<19)
+#define S3C2410_TCON_T3INVERT    (1<<18)
+#define S3C2410_TCON_T3MANUALUPD  (1<<17)
+#define S3C2410_TCON_T3START     (1<<16)
+
+#define S3C2410_TCON_T2RELOAD    (1<<15)
+#define S3C2410_TCON_T2INVERT    (1<<14)
+#define S3C2410_TCON_T2MANUALUPD  (1<<13)
+#define S3C2410_TCON_T2START     (1<<12)
+
+#define S3C2410_TCON_T1RELOAD    (1<<11)
+#define S3C2410_TCON_T1INVERT    (1<<10)
+#define S3C2410_TCON_T1MANUALUPD  (1<<9)
+#define S3C2410_TCON_T1START     (1<<8)
+
+#define S3C2410_TCON_T0DEADZONE          (1<<4)
+#define S3C2410_TCON_T0RELOAD    (1<<3)
+#define S3C2410_TCON_T0INVERT    (1<<2)
+#define S3C2410_TCON_T0MANUALUPD  (1<<1)
+#define S3C2410_TCON_T0START     (1<<0)
+
+#endif /*  __ASM_ARCH_REGS_TIMER_H */
+
+
+

diff --git a/include/asm-arm/plat-s3c/regs-watchdog.h b/include/asm-arm/plat-s3c/regs-watchdog.h
new file mode 100644 (file)
index 0000000..a9c5d49
--- /dev/null
+++ b/include/asm-arm/plat-s3c/regs-watchdog.h
@@ -0,0 +1,41 @@
+/* linux/include/asm-arm/arch-s3c2410/regs-watchdog.h
+ *
+ * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
+ *                   http://www.simtec.co.uk/products/SWLINUX/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * S3C2410 Watchdog timer control
+*/
+
+
+#ifndef __ASM_ARCH_REGS_WATCHDOG_H
+#define __ASM_ARCH_REGS_WATCHDOG_H "$Id: watchdog.h,v 1.2 2003/04/29 13:31:09 ben Exp $"
+
+#define S3C2410_WDOGREG(x) ((x) + S3C24XX_VA_WATCHDOG)
+
+#define S3C2410_WTCON     S3C2410_WDOGREG(0x00)
+#define S3C2410_WTDAT     S3C2410_WDOGREG(0x04)
+#define S3C2410_WTCNT     S3C2410_WDOGREG(0x08)
+
+/* the watchdog can either generate a reset pulse, or an
+ * interrupt.
+ */
+
+#define S3C2410_WTCON_RSTEN   (0x01)
+#define S3C2410_WTCON_INTEN   (1<<2)
+#define S3C2410_WTCON_ENABLE  (1<<5)
+
+#define S3C2410_WTCON_DIV16   (0<<3)
+#define S3C2410_WTCON_DIV32   (1<<3)
+#define S3C2410_WTCON_DIV64   (2<<3)
+#define S3C2410_WTCON_DIV128  (3<<3)
+
+#define S3C2410_WTCON_PRESCALE(x) ((x) << 8)
+#define S3C2410_WTCON_PRESCALE_MASK (0xff00)
+
+#endif /* __ASM_ARCH_REGS_WATCHDOG_H */
+
+