On G965, I810_PGETBL_CTL is a mmio offset, but we wrongly take it
as pci config space offset in detecting GTT size. This one line patch
fixs this.
Signed-off-by: Wang Zhenyu <zhenyu.z.wang@intel.com>
Signed-off-by: Dave Jones <davej@redhat.com>
if (IS_I965) {
u32 pgetbl_ctl;
+ pgetbl_ctl = readl(intel_i830_private.registers+I810_PGETBL_CTL);
- pci_read_config_dword(agp_bridge->dev, I810_PGETBL_CTL,
- &pgetbl_ctl);
/* The 965 has a field telling us the size of the GTT,
* which may be larger than what is necessary to map the
* aperture.