drm/msm/dpu: remove dpu_hw_pipe_cdp_cfg from dpu_plane

Remove struct dpu_hw_pipe_cdp_cfg instance from dpu_plane, it is an
interim configuration structure. Allocate it on stack instead.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org>
Link: https://lore.kernel.org/r/20210930140002.308628-9-dmitry.baryshkov@linaro.org
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Rob Clark <robdclark@chromium.org>

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
index 0da88f6..6c3ad1b 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c
@@ -1189,20 +1189,20 @@ static void dpu_plane_sspp_atomic_update(struct drm_plane *plane)
                                pstate->multirect_index);
 
                if (pdpu->pipe_hw->ops.setup_cdp) {
-                       struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
+                       struct dpu_hw_pipe_cdp_cfg cdp_cfg;
 
-                       memset(cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
+                       memset(&cdp_cfg, 0, sizeof(struct dpu_hw_pipe_cdp_cfg));
 
-                       cdp_cfg->enable = pdpu->catalog->perf.cdp_cfg
+                       cdp_cfg.enable = pdpu->catalog->perf.cdp_cfg
                                        [DPU_PERF_CDP_USAGE_RT].rd_enable;
-                       cdp_cfg->ubwc_meta_enable =
+                       cdp_cfg.ubwc_meta_enable =
                                        DPU_FORMAT_IS_UBWC(fmt);
-                       cdp_cfg->tile_amortize_enable =
+                       cdp_cfg.tile_amortize_enable =
                                        DPU_FORMAT_IS_UBWC(fmt) ||
                                        DPU_FORMAT_IS_TILE(fmt);
-                       cdp_cfg->preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
+                       cdp_cfg.preload_ahead = DPU_SSPP_CDP_PRELOAD_AHEAD_64;
 
-                       pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, cdp_cfg);
+                       pdpu->pipe_hw->ops.setup_cdp(pdpu->pipe_hw, &cdp_cfg);
                }
        }
 

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
index 34e03ac..5279252 100644 (file)
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h
@@ -25,7 +25,6 @@
  * @pending:   whether the current update is still pending
  * @scaler3_cfg: configuration data for scaler3
  * @pixel_ext: configuration data for pixel extensions
- * @cdp_cfg:   CDP configuration
  * @plane_fetch_bw: calculated BW per plane
  * @plane_clk: calculated clk per plane
  */
@@ -42,7 +41,6 @@ struct dpu_plane_state {
        struct dpu_hw_scaler3_cfg scaler3_cfg;
        struct dpu_hw_pixel_ext pixel_ext;
 
-       struct dpu_hw_pipe_cdp_cfg cdp_cfg;
        u64 plane_fetch_bw;
        u64 plane_clk;
 };