drm/amd/display: assume VBIOS supports DSC as default
authorCharlene Liu <Charlene.Liu@amd.com>
Thu, 27 Feb 2025 04:52:57 +0000 (23:52 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Mon, 10 Mar 2025 17:28:41 +0000 (13:28 -0400)
[Why & How]
The clear_dsc_setting at boot logic was based on dcn version
check.
As such new ASIC lost this DSC clear up logic, change the
assumption to BIOS support eDP DSC for new ASIC.

Reviewed-by: Alvin Lee <alvin.lee2@amd.com>
Signed-off-by: Charlene Liu <Charlene.Liu@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/display/dc/hwss/dce110/dce110_hwseq.c

index bfd734e..dbc6e53 100644 (file)
@@ -1836,11 +1836,10 @@ static void clean_up_dsc_blocks(struct dc *dc)
        struct pg_cntl *pg_cntl = dc->res_pool->pg_cntl;
        int i;
 
-       if (dc->ctx->dce_version != DCN_VERSION_3_5 &&
-               dc->ctx->dce_version != DCN_VERSION_3_6 &&
-               dc->ctx->dce_version != DCN_VERSION_3_51)
+       if (!dc->caps.is_apu ||
+               dc->ctx->dce_version < DCN_VERSION_3_15)
                return;
-
+       /*VBIOS supports dsc starts from dcn315*/
        for (i = 0; i < dc->res_pool->res_cap->num_dsc; i++) {
                struct dcn_dsc_state s  = {0};