ARM: dts: rockchip: add gpu nodes on rk3066/rk3188

The old Cortex-A9 socs use Mali400 GPUs with 4 pixel processors.
This adds the core gpu nodes with the per-soc interrupts but sharing
the core node.

Rockchip SoCs use only one clock to supply the GPUs

Signed-off-by: Heiko Stuebner <heiko@sntech.de>

diff --git a/arch/arm/boot/dts/rk3066a.dtsi b/arch/arm/boot/dts/rk3066a.dtsi
index f50481f..b76119d 100644 (file)
--- a/arch/arm/boot/dts/rk3066a.dtsi
+++ b/arch/arm/boot/dts/rk3066a.dtsi
@@ -610,6 +610,30 @@
        };
 };
 
+&gpu {
+       compatible = "rockchip,rk3066-mali", "arm,mali-400";
+       interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
+       interrupt-names = "gp",
+                         "gpmmu",
+                         "pp0",
+                         "pp0mmu",
+                         "pp1",
+                         "pp1mmu",
+                         "pp2",
+                         "pp2mmu",
+                         "pp3",
+                         "pp3mmu";
+};
+
 &i2c0 {
        pinctrl-names = "default";
        pinctrl-0 = <&i2c0_xfer>;

diff --git a/arch/arm/boot/dts/rk3188.dtsi b/arch/arm/boot/dts/rk3188.dtsi
index 1399bc0..9e24d0f 100644 (file)
--- a/arch/arm/boot/dts/rk3188.dtsi
+++ b/arch/arm/boot/dts/rk3188.dtsi
@@ -553,6 +553,30 @@
        interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
 };
 
+&gpu {
+       compatible = "rockchip,rk3188-mali", "arm,mali-400";
+       interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
+                    <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
+       interrupt-names = "gp",
+                         "gpmmu",
+                         "pp0",
+                         "pp0mmu",
+                         "pp1",
+                         "pp1mmu",
+                         "pp2",
+                         "pp2mmu",
+                         "pp3",
+                         "pp3mmu";
+};
+
 &i2c0 {
        compatible = "rockchip,rk3188-i2c";
        pinctrl-names = "default";

diff --git a/arch/arm/boot/dts/rk3xxx.dtsi b/arch/arm/boot/dts/rk3xxx.dtsi
index 4aa6f60..49584b6 100644 (file)
--- a/arch/arm/boot/dts/rk3xxx.dtsi
+++ b/arch/arm/boot/dts/rk3xxx.dtsi
@@ -117,6 +117,17 @@
                clock-output-names = "xin24m";
        };
 
+       gpu: gpu@10090000 {
+               compatible = "arm,mali-400";
+               reg = <0x10090000 0x10000>;
+               clocks = <&cru ACLK_GPU>, <&cru ACLK_GPU>;
+               clock-names = "core", "bus";
+               assigned-clocks = <&cru ACLK_GPU>;
+               assigned-clock-rates = <100000000>;
+               resets = <&cru SRST_GPU>;
+               status = "disabled";
+       };
+
        L2: l2-cache-controller@10138000 {
                compatible = "arm,pl310-cache";
                reg = <0x10138000 0x1000>;