drm/amd/display: Init DPPCLK from SMU on dcn32

[WHY & HOW]
DPPCLK ranges should be obtained from the SMU when available.

Cc: Mario Limonciello <mario.limonciello@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Dillon Varone <dillon.varone@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
index 668f05c..bec252e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
+++ b/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/dcn32_clk_mgr.c
@@ -216,6 +216,16 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
        if (clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz > 1950)
                clk_mgr_base->bw_params->dc_mode_limit.dispclk_mhz = 1950;
 
+       /* DPPCLK */
+       dcn32_init_single_clock(clk_mgr, PPCLK_DPPCLK,
+                       &clk_mgr_base->bw_params->clk_table.entries[0].dppclk_mhz,
+                       &num_entries_per_clk->num_dppclk_levels);
+       num_levels = num_entries_per_clk->num_dppclk_levels;
+       clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = dcn30_smu_get_dc_mode_max_dpm_freq(clk_mgr, PPCLK_DPPCLK);
+       //HW recommends limit of 1950 MHz in display clock for all DCN3.2.x
+       if (clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz > 1950)
+               clk_mgr_base->bw_params->dc_mode_limit.dppclk_mhz = 1950;
+
        if (num_entries_per_clk->num_dcfclk_levels &&
                        num_entries_per_clk->num_dtbclk_levels &&
                        num_entries_per_clk->num_dispclk_levels)
@@ -240,6 +250,10 @@ void dcn32_init_clocks(struct clk_mgr *clk_mgr_base)
                                        = khz_to_mhz_ceil(clk_mgr_base->ctx->dc->debug.min_dpp_clk_khz);
        }
 
+       for (i = 0; i < num_levels; i++)
+               if (clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz > 1950)
+                       clk_mgr_base->bw_params->clk_table.entries[i].dppclk_mhz = 1950;
+
        /* Get UCLK, update bounding box */
        clk_mgr_base->funcs->get_memclk_states_from_smu(clk_mgr_base);
 

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
index 2a58a76..72cca36 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.c
@@ -703,13 +703,8 @@ static inline struct dml2_context *dml2_allocate_memory(void)
        return (struct dml2_context *) kzalloc(sizeof(struct dml2_context), GFP_KERNEL);
 }
 
-bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
+static void dml2_init(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
 {
-       // Allocate Mode Lib Ctx
-       *dml2 = dml2_allocate_memory();
-
-       if (!(*dml2))
-               return false;
 
        // Store config options
        (*dml2)->config = *config;
@@ -737,9 +732,18 @@ bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options
        initialize_dml2_soc_bbox(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc);
 
        initialize_dml2_soc_states(*dml2, in_dc, &(*dml2)->v20.dml_core_ctx.soc, &(*dml2)->v20.dml_core_ctx.states);
+}
+
+bool dml2_create(const struct dc *in_dc, const struct dml2_configuration_options *config, struct dml2_context **dml2)
+{
+       // Allocate Mode Lib Ctx
+       *dml2 = dml2_allocate_memory();
+
+       if (!(*dml2))
+               return false;
+
+       dml2_init(in_dc, config, dml2);
 
-       /*Initialize DML20 instance which calls dml2_core_create, and core_dcn3_populate_informative*/
-       //dml2_initialize_instance(&(*dml_ctx)->v20.dml_init);
        return true;
 }
 
@@ -779,3 +783,11 @@ bool dml2_create_copy(struct dml2_context **dst_dml2,
 
        return true;
 }
+
+void dml2_reinit(const struct dc *in_dc,
+                                const struct dml2_configuration_options *config,
+                                struct dml2_context **dml2)
+{
+
+       dml2_init(in_dc, config, dml2);
+}

diff --git a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
index ee0eb18..cc662d6 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
+++ b/drivers/gpu/drm/amd/display/dc/dml2/dml2_wrapper.h
@@ -214,6 +214,9 @@ void dml2_copy(struct dml2_context *dst_dml2,
        struct dml2_context *src_dml2);
 bool dml2_create_copy(struct dml2_context **dst_dml2,
        struct dml2_context *src_dml2);
+void dml2_reinit(const struct dc *in_dc,
+                                const struct dml2_configuration_options *config,
+                                struct dml2_context **dml2);
 
 /*
  * dml2_validate - Determines if a display configuration is supported or not.

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
index f844f57..ce1754c 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn32/dcn32_resource.c
@@ -1931,6 +1931,8 @@ static void dcn32_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *bw
 {
        DC_FP_START();
        dcn32_update_bw_bounding_box_fpu(dc, bw_params);
+       if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
+               dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
        DC_FP_END();
 }
 

diff --git a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
index b356fed..296a0a8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/resource/dcn321/dcn321_resource.c
@@ -1581,6 +1581,8 @@ static void dcn321_update_bw_bounding_box(struct dc *dc, struct clk_bw_params *b
 {
        DC_FP_START();
        dcn321_update_bw_bounding_box_fpu(dc, bw_params);
+       if (dc->debug.using_dml2 && dc->current_state && dc->current_state->bw_ctx.dml2)
+               dml2_reinit(dc, &dc->dml2_options, &dc->current_state->bw_ctx.dml2);
        DC_FP_END();
 }