octeontx2-af: debugfs: update CQ context fields

This patch update the CQ structure fields to support the feature
added in new silicons and also dump these fields in debugfs.

Signed-off-by: Nithin Dabilpuram <ndabilpuram@marvell.com>
Signed-off-by: Geetha sowjanya <gakula@marvell.com>
Link: https://lore.kernel.org/r/20231130060703.16769-1-gakula@marvell.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
index 468b656..e6d7914 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_debugfs.c
@@ -1825,6 +1825,8 @@ static void print_nix_rq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)
 static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)
 {
        struct nix_cq_ctx_s *cq_ctx = &rsp->cq;
+       struct nix_hw *nix_hw = m->private;
+       struct rvu *rvu = nix_hw->rvu;
 
        seq_printf(m, "W0: base \t\t\t%llx\n\n", cq_ctx->base);
 
@@ -1836,6 +1838,16 @@ static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)
        seq_printf(m, "W1: bpid \t\t\t%d\nW1: bp_ena \t\t\t%d\n\n",
                   cq_ctx->bpid, cq_ctx->bp_ena);
 
+       if (!is_rvu_otx2(rvu)) {
+               seq_printf(m, "W1: lbpid_high \t\t\t0x%03x\n", cq_ctx->lbpid_high);
+               seq_printf(m, "W1: lbpid_med \t\t\t0x%03x\n", cq_ctx->lbpid_med);
+               seq_printf(m, "W1: lbpid_low \t\t\t0x%03x\n", cq_ctx->lbpid_low);
+               seq_printf(m, "(W1: lbpid) \t\t\t0x%03x\n",
+                          cq_ctx->lbpid_high << 6 | cq_ctx->lbpid_med << 3 |
+                          cq_ctx->lbpid_low);
+               seq_printf(m, "W1: lbp_ena \t\t\t\t%d\n\n", cq_ctx->lbp_ena);
+       }
+
        seq_printf(m, "W2: update_time \t\t%d\nW2:avg_level \t\t\t%d\n",
                   cq_ctx->update_time, cq_ctx->avg_level);
        seq_printf(m, "W2: head \t\t\t%d\nW2:tail \t\t\t%d\n\n",
@@ -1847,6 +1859,11 @@ static void print_nix_cq_ctx(struct seq_file *m, struct nix_aq_enq_rsp *rsp)
                   cq_ctx->qsize, cq_ctx->caching);
        seq_printf(m, "W3: substream \t\t\t0x%03x\nW3: ena \t\t\t%d\n",
                   cq_ctx->substream, cq_ctx->ena);
+       if (!is_rvu_otx2(rvu)) {
+               seq_printf(m, "W3: lbp_frac \t\t\t%d\n", cq_ctx->lbp_frac);
+               seq_printf(m, "W3: cpt_drop_err_en \t\t\t%d\n",
+                          cq_ctx->cpt_drop_err_en);
+       }
        seq_printf(m, "W3: drop_ena \t\t\t%d\nW3: drop \t\t\t%d\n",
                   cq_ctx->drop_ena, cq_ctx->drop);
        seq_printf(m, "W3: bp \t\t\t\t%d\n\n", cq_ctx->bp);

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
index edc9367..5ef406c 100644 (file)
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_struct.h
@@ -340,11 +340,12 @@ struct nix_aq_res_s {
 /* NIX Completion queue context structure */
 struct nix_cq_ctx_s {
        u64 base;
-       u64 rsvd_64_67          : 4;
+       u64 lbp_ena             : 1;
+       u64 lbpid_low           : 3;
        u64 bp_ena              : 1;
-       u64 rsvd_69_71          : 3;
+       u64 lbpid_med           : 3;
        u64 bpid                : 9;
-       u64 rsvd_81_83          : 3;
+       u64 lbpid_high          : 3;
        u64 qint_idx            : 7;
        u64 cq_err              : 1;
        u64 cint_idx            : 7;
@@ -358,10 +359,14 @@ struct nix_cq_ctx_s {
        u64 drop                : 8;
        u64 drop_ena            : 1;
        u64 ena                 : 1;
-       u64 rsvd_210_211        : 2;
-       u64 substream           : 20;
+       u64 cpt_drop_err_en     : 1;
+       u64 rsvd_211            : 1;
+       u64 substream           : 12;
+       u64 stash_thresh        : 4;
+       u64 lbp_frac            : 4;
        u64 caching             : 1;
-       u64 rsvd_233_235        : 3;
+       u64 stashing            : 1;
+       u64 rsvd_234_235        : 2;
        u64 qsize               : 4;
        u64 cq_err_int          : 8;
        u64 cq_err_int_ena      : 8;