*/
 }
 
+static void gen9_set_dc_state_debugmask_memory_up(
+                       struct drm_i915_private *dev_priv)
+{
+       uint32_t val;
+
+       /* The below bit doesn't need to be cleared ever afterwards */
+       val = I915_READ(DC_STATE_DEBUG);
+       if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
+               val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
+               I915_WRITE(DC_STATE_DEBUG, val);
+               POSTING_READ(DC_STATE_DEBUG);
+       }
+}
+
 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 {
        uint32_t val;
 
        WARN_ON_ONCE(state & ~mask);
 
+       if (state & DC_STATE_EN_UPTO_DC5_DC6_MASK)
+               gen9_set_dc_state_debugmask_memory_up(dev_priv);
+
        val = I915_READ(DC_STATE_EN);
        DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
                      val & mask, state);
        gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 }
 
-static void gen9_set_dc_state_debugmask_memory_up(
-                       struct drm_i915_private *dev_priv)
-{
-       uint32_t val;
-
-       /* The below bit doesn't need to be cleared ever afterwards */
-       val = I915_READ(DC_STATE_DEBUG);
-       if (!(val & DC_STATE_DEBUG_MASK_MEMORY_UP)) {
-               val |= DC_STATE_DEBUG_MASK_MEMORY_UP;
-               I915_WRITE(DC_STATE_DEBUG, val);
-               POSTING_READ(DC_STATE_DEBUG);
-       }
-}
-
 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 {
        WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 
        DRM_DEBUG_KMS("Enabling DC5\n");
 
-       gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
        gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 }
 
 
        DRM_DEBUG_KMS("Enabling DC6\n");
 
-       gen9_set_dc_state_debugmask_memory_up(dev_priv);
-
        gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 
 }