return ret;
}
+static int smu_v15_0_0_get_enabled_mask(struct smu_context *smu,
+ struct smu_feature_bits *feature_mask)
+{
+ int ret;
+ struct smu_msg_ctl *ctl = &smu->msg_ctl;
+
+ if (!feature_mask)
+ return -EINVAL;
+
+ struct smu_msg_args args = {
+ .msg = SMU_MSG_GetEnabledSmuFeatures,
+ .num_args = 0,
+ .num_out_args = 2,
+ };
+
+ ret = ctl->ops->send_msg(ctl, &args);
+
+ if (!ret)
+ smu_feature_bits_from_arr32(feature_mask, args.out_args,
+ SMU_FEATURE_NUM_DEFAULT);
+
+ return ret;
+}
+
static bool smu_v15_0_0_is_dpm_running(struct smu_context *smu)
{
int ret = 0;
struct smu_feature_bits feature_enabled;
- ret = smu_cmn_get_enabled_mask(smu, &feature_enabled);
+ ret = smu_v15_0_0_get_enabled_mask(smu, &feature_enabled);
if (ret)
return false;
.is_dpm_running = smu_v15_0_0_is_dpm_running,
.set_watermarks_table = smu_v15_0_0_set_watermarks_table,
.get_gpu_metrics = smu_v15_0_0_get_gpu_metrics,
- .get_enabled_mask = smu_cmn_get_enabled_mask,
+ .get_enabled_mask = smu_v15_0_0_get_enabled_mask,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_driver_table_location = smu_v15_0_set_driver_table_location,
.gfx_off_control = smu_v15_0_gfx_off_control,