drm/amd/display: Migrate DCCG registers access from hwseq to dccg component.

[Why]
Direct DCCG register access in hwseq layer was creating register conflicts.

[How]
Migrated DCCG registers from hwseq-dccg component.

Reviewed-by: Martin Leung <Martin.Leung@amd.com>
Signed-off-by: Bhuvanachandra Pinninti <BhuvanaChandra.Pinninti@amd.com>
Signed-off-by: Ray Wu <ray.wu@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
index 33d8bd9..733b85d 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.c
@@ -131,6 +131,54 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
 
 void dccg2_init(struct dccg *dccg)
 {
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       /* Hardcoded register values for DCN20
+        * These are specific to 100Mhz refclk
+        * Different ASICs with different refclk may override this in their own init
+        */
+       REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x00120264);
+       REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x001186a0);
+       REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0x0e01003c);
+
+       if (REG(REFCLK_CNTL))
+               REG_WRITE(REFCLK_CNTL, 0);
+}
+
+void dccg2_refclk_setup(struct dccg *dccg)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       /* REFCLK programming that must occur after hubbub initialization */
+       if (REG(REFCLK_CNTL))
+               REG_WRITE(REFCLK_CNTL, 0);
+}
+
+bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       return REG_READ(MICROSECOND_TIME_BASE_DIV) == 0x00120464;
+}
+
+void dccg2_allow_clock_gating(struct dccg *dccg, bool allow)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       if (allow) {
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+       } else {
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0xFFFFFFFF);
+               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0xFFFFFFFF);
+       }
+}
+
+void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable)
+{
+       struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
+
+       REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, enable ? 0 : 1);
 }
 
 static const struct dccg_funcs dccg2_funcs = {
@@ -139,7 +187,11 @@ static const struct dccg_funcs dccg2_funcs = {
        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .otg_add_pixel = dccg2_otg_add_pixel,
        .otg_drop_pixel = dccg2_otg_drop_pixel,
-       .dccg_init = dccg2_init
+       .dccg_init = dccg2_init,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg2_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
index 8bdffd9..3711d40 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
@@ -37,7 +37,8 @@
        SR(REFCLK_CNTL),\
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 0),\
        DCCG_SRII(PIXEL_RATE_CNTL, OTG, 1),\
-       SR(DISPCLK_FREQ_CHANGE_CNTL)
+       SR(DISPCLK_FREQ_CHANGE_CNTL),\
+       SR(DC_MEM_GLOBAL_PWR_REQ_CNTL)
 
 #define DCCG_REG_LIST_DCN2() \
        DCCG_COMMON_REG_LIST_DCN_BASE(),\
@@ -81,7 +82,8 @@
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 0, mask_sh),\
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, ADD_PIXEL, 1, mask_sh),\
        DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 0, mask_sh),\
-       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh)
+       DCCG_SFII(OTG, PIXEL_RATE_CNTL, OTG, DROP_PIXEL, 1, mask_sh),\
+       DCCG_SF(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, mask_sh)
 
 
 
@@ -130,7 +132,8 @@
        type DISPCLK_CHG_FWD_CORR_DISABLE;\
        type DISPCLK_FREQ_CHANGE_CNTL;\
        type OTG_ADD_PIXEL[MAX_PIPES];\
-       type OTG_DROP_PIXEL[MAX_PIPES];
+       type OTG_DROP_PIXEL[MAX_PIPES];\
+       type DC_MEM_GLOBAL_PWR_REQ_DIS;
 
 #define DCCG3_REG_FIELD_LIST(type) \
        type HDMICHARCLK0_EN;\
@@ -515,6 +518,11 @@ void dccg2_otg_drop_pixel(struct dccg *dccg,
 
 void dccg2_init(struct dccg *dccg);
 
+void dccg2_refclk_setup(struct dccg *dccg);
+void dccg2_allow_clock_gating(struct dccg *dccg, bool allow);
+void dccg2_enable_memory_low_power(struct dccg *dccg, bool enable);
+bool dccg2_is_s0i3_golden_init_wa_done(struct dccg *dccg);
+
 struct dccg *dccg2_create(
        struct dc_context *ctx,
        const struct dccg_registers *regs,

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c
index 9a34021..79d14ce 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn201/dcn201_dccg.c
@@ -24,6 +24,7 @@
  */
 
 #include "dcn201_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 #include "reg_helper.h"
 #include "core_types.h"
@@ -56,7 +57,11 @@ static const struct dccg_funcs dccg201_funcs = {
        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .otg_add_pixel = dccg2_otg_add_pixel,
        .otg_drop_pixel = dccg2_otg_drop_pixel,
-       .dccg_init = dccg2_init
+       .dccg_init = dccg2_init,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg201_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
index d07c044..b48dcaf 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn21/dcn21_dccg.c
@@ -103,7 +103,11 @@ static const struct dccg_funcs dccg21_funcs = {
        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .otg_add_pixel = dccg2_otg_add_pixel,
        .otg_drop_pixel = dccg2_otg_drop_pixel,
-       .dccg_init = dccg2_init
+       .dccg_init = dccg2_init,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg21_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c
index d445dfe..adec7c3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn30/dcn30_dccg.c
@@ -49,7 +49,11 @@ static const struct dccg_funcs dccg3_funcs = {
        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .otg_add_pixel = dccg2_otg_add_pixel,
        .otg_drop_pixel = dccg2_otg_drop_pixel,
-       .dccg_init = dccg2_init
+       .dccg_init = dccg2_init,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg3_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c
index 97e9be8..fc9bddd 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn301/dcn301_dccg.c
@@ -48,7 +48,11 @@ static const struct dccg_funcs dccg301_funcs = {
        .set_fifo_errdet_ovr_en = dccg2_set_fifo_errdet_ovr_en,
        .otg_add_pixel = dccg2_otg_add_pixel,
        .otg_drop_pixel = dccg2_otg_drop_pixel,
-       .dccg_init = dccg2_init
+       .dccg_init = dccg2_init,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg301_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
index 97df04b..c647dff 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
@@ -26,6 +26,7 @@
 #include "reg_helper.h"
 #include "core_types.h"
 #include "dcn31_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 #include "dal_asic_id.h"
 
 #define TO_DCN_DCCG(dccg)\
@@ -850,6 +851,10 @@ static const struct dccg_funcs dccg31_funcs = {
        .disable_dsc = dccg31_disable_dscclk,
        .enable_dsc = dccg31_enable_dscclk,
        .dccg_read_reg_state = dccg31_read_reg_state,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg31_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
index ef3db6b..2e9c4b1 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
@@ -29,6 +29,7 @@
 
 #include "dcn31/dcn31_dccg.h"
 #include "dcn314_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 #define TO_DCN_DCCG(dccg)\
        container_of(dccg, struct dcn_dccg, base)
@@ -378,7 +379,11 @@ static const struct dccg_funcs dccg314_funcs = {
        .trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,
        .set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
        .set_dtbclk_p_src = dccg314_set_dtbclk_p_src,
-       .dccg_read_reg_state = dccg31_read_reg_state
+       .dccg_read_reg_state = dccg31_read_reg_state,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg314_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
index 21a6ca5..ce697c3 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn32/dcn32_dccg.c
@@ -26,6 +26,7 @@
 #include "reg_helper.h"
 #include "core_types.h"
 #include "dcn32_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 #define TO_DCN_DCCG(dccg)\
        container_of(dccg, struct dcn_dccg, base)
@@ -347,6 +348,10 @@ static const struct dccg_funcs dccg32_funcs = {
        .get_pixel_rate_div = dccg32_get_pixel_rate_div,
        .trigger_dio_fifo_resync = dccg32_trigger_dio_fifo_resync,
        .set_dtbclk_p_src = dccg32_set_dtbclk_p_src,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 struct dccg *dccg32_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
index 838c661..943ec19 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
@@ -26,6 +26,7 @@
 #include "core_types.h"
 #include "resource.h"
 #include "dcn35_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 #define TO_DCN_DCCG(dccg)\
        container_of(dccg, struct dcn_dccg, base)
@@ -2411,6 +2412,10 @@ static const struct dccg_funcs dccg35_funcs_new = {
        .enable_symclk_se = dccg35_enable_symclk_se_cb,
        .disable_symclk_se = dccg35_disable_symclk_se_cb,
        .set_dtbclk_p_src = dccg35_set_dtbclk_p_src_cb,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done /* Deprecated - for backward compatibility only */
 };
 
 static const struct dccg_funcs dccg35_funcs = {
@@ -2442,8 +2447,12 @@ static const struct dccg_funcs dccg35_funcs = {
        .enable_symclk_se = dccg35_enable_symclk_se,
        .disable_symclk_se = dccg35_disable_symclk_se,
        .set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
+       .refclk_setup = dccg2_refclk_setup, /* Deprecated - for backward compatibility only */
+       .allow_clock_gating = dccg2_allow_clock_gating,
+       .enable_memory_low_power = dccg2_enable_memory_low_power,
+       .is_s0i3_golden_init_wa_done = dccg2_is_s0i3_golden_init_wa_done, /* Deprecated - for backward compatibility only */
        .dccg_root_gate_disable_control = dccg35_root_gate_disable_control,
-       .dccg_read_reg_state = dccg31_read_reg_state,
+       .dccg_read_reg_state = dccg31_read_reg_state
 };
 
 struct dccg *dccg35_create(

diff --git a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
index 3063b6a..f1d3945 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+++ b/drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
@@ -27,6 +27,7 @@
 #include "core_types.h"
 #include "dcn401_dccg.h"
 #include "dcn31/dcn31_dccg.h"
+#include "dcn20/dcn20_dccg.h"
 
 /*
 #include "dmub_common.h"
@@ -861,6 +862,7 @@ static const struct dccg_funcs dccg401_funcs = {
        .update_dpp_dto = dccg401_update_dpp_dto,
        .get_dccg_ref_freq = dccg401_get_dccg_ref_freq,
        .dccg_init = dccg401_init,
+       .allow_clock_gating = dccg2_allow_clock_gating,
        .set_dpstreamclk = dccg401_set_dpstreamclk,
        .enable_symclk32_se = dccg31_enable_symclk32_se,
        .disable_symclk32_se = dccg31_disable_symclk32_se,

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
index 9613d1c..5243177 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn10/dcn10_hwseq.c
@@ -1887,9 +1887,8 @@ void dcn10_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
index 0ee3a00..307e8f8 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn20/dcn20_hwseq.c
@@ -357,26 +357,10 @@ void dcn20_enable_power_gating_plane(
 
 void dcn20_dccg_init(struct dce_hwseq *hws)
 {
-       /*
-        * set MICROSECOND_TIME_BASE_DIV
-        * 100Mhz refclk -> 0x120264
-        * 27Mhz refclk -> 0x12021b
-        * 48Mhz refclk -> 0x120230
-        *
-        */
-       REG_WRITE(MICROSECOND_TIME_BASE_DIV, 0x120264);
-
-       /*
-        * set MILLISECOND_TIME_BASE_DIV
-        * 100Mhz refclk -> 0x1186a0
-        * 27Mhz refclk -> 0x106978
-        * 48Mhz refclk -> 0x10bb80
-        *
-        */
-       REG_WRITE(MILLISECOND_TIME_BASE_DIV, 0x1186a0);
+       struct dc *dc = hws->ctx->dc;
 
-       /* This value is dependent on the hardware pipeline delay so set once per SOC */
-       REG_WRITE(DISPCLK_FREQ_CHANGE_CNTL, 0xe01003c);
+       if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->dccg_init)
+               dc->res_pool->dccg->funcs->dccg_init(dc->res_pool->dccg);
 }
 
 void dcn20_disable_vga(
@@ -3156,8 +3140,11 @@ void dcn20_fpga_init_hw(struct dc *dc)
 
        dcn10_hubbub_global_timer_enable(dc->res_pool->hubbub, true, 2);
 
-       if (REG(REFCLK_CNTL))
-               REG_WRITE(REFCLK_CNTL, 0);
+       if (hws->funcs.dccg_init)
+               hws->funcs.dccg_init(hws);
+
+       if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->refclk_setup)
+               dc->res_pool->dccg->funcs->refclk_setup(dc->res_pool->dccg);
        //
 
 

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
index 6298bd8..ce18d75 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn201/dcn201_hwseq.c
@@ -367,9 +367,8 @@ void dcn201_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
index e226921..0627453 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn21/dcn21_hwseq.c
@@ -33,6 +33,7 @@
 #include "vmid.h"
 #include "reg_helper.h"
 #include "hw/clk_mgr.h"
+#include "hw/dccg.h"
 #include "dc_dmub_srv.h"
 #include "abm.h"
 #include "link_service.h"
@@ -87,12 +88,10 @@ int dcn21_init_sys_ctx(struct dce_hwseq *hws, struct dc *dc, struct dc_phy_addr_
 
 bool dcn21_s0i3_golden_init_wa(struct dc *dc)
 {
-       struct dce_hwseq *hws = dc->hwseq;
-       uint32_t value = 0;
+       if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done)
+               return !dc->res_pool->dccg->funcs->is_s0i3_golden_init_wa_done(dc->res_pool->dccg);
 
-       value = REG_READ(MICROSECOND_TIME_BASE_DIV);
-
-       return value != 0x00120464;
+       return false;
 }
 
 void dcn21_exit_optimized_pwr_state(

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
index 3332750..d04cfd4 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn30/dcn30_hwseq.c
@@ -801,9 +801,8 @@ void dcn30_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
index fa35d53..db2f7cb 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn31/dcn31_hwseq.c
@@ -247,9 +247,8 @@ void dcn31_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
index 01fa459..2767d3a 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_hwseq.c
@@ -963,9 +963,8 @@ void dcn32_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
index 0cbd75a..b5a4cef 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn35/dcn35_hwseq.c
@@ -286,7 +286,8 @@ void dcn35_init_hw(struct dc *dc)
        }
 
        if (dc->debug.disable_mem_low_power) {
-               REG_UPDATE(DC_MEM_GLOBAL_PWR_REQ_CNTL, DC_MEM_GLOBAL_PWR_REQ_DIS, 1);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->enable_memory_low_power)
+                       dc->res_pool->dccg->funcs->enable_memory_low_power(dc->res_pool->dccg, false);
        }
        if (!dcb->funcs->is_accelerated_mode(dcb) && dc->res_pool->hubbub->funcs->init_watermarks)
                dc->res_pool->hubbub->funcs->init_watermarks(dc->res_pool->hubbub);

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index d151503..b91517b 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -326,9 +326,8 @@ void dcn401_init_hw(struct dc *dc)
 
        if (!dc->debug.disable_clock_gate) {
                /* enable all DCN clock gating */
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL, 0);
-
-               REG_WRITE(DCCG_GATE_DISABLE_CNTL2, 0);
+               if (dc->res_pool->dccg && dc->res_pool->dccg->funcs && dc->res_pool->dccg->funcs->allow_clock_gating)
+                       dc->res_pool->dccg->funcs->allow_clock_gating(dc->res_pool->dccg, true);
 
                REG_UPDATE(DCFCLK_CNTL, DCFCLK_GATE_DIS, 0);
        }

diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
index 1e6ffd8..d6f5e01 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
+++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h
@@ -224,6 +224,10 @@ struct dccg_funcs {
        void (*otg_drop_pixel)(struct dccg *dccg,
                        uint32_t otg_inst);
        void (*dccg_init)(struct dccg *dccg);
+       void (*refclk_setup)(struct dccg *dccg); /* Deprecated - for backward compatibility only */
+       void (*allow_clock_gating)(struct dccg *dccg, bool allow);
+       void (*enable_memory_low_power)(struct dccg *dccg, bool enable);
+       bool (*is_s0i3_golden_init_wa_done)(struct dccg *dccg);
        void (*set_dpstreamclk_root_clock_gating)(
                        struct dccg *dccg,
                        int dp_hpo_inst,