drm/i915/tgl: Add Wa_22010178259:tgl

We need to explicitly set the TLB Request Timer initial value in the
BW_BUDDY registers to 0x8 rather than relying on the hardware default.

v2: Apply missing REG_FIELD_PREP to ensure 0x8 is placed in the correct
    bits during the rmw.  (Jose)

Bspec: 52890
Bspec: 50044
Fixes: 3fa01d642fa7 ("drm/i915/tgl: Program BW_BUDDY registers during display init")
Cc: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200219215655.2923650-1-matthew.d.roper@intel.com
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
(cherry picked from commit 87e04f75928bb5d357ef7df4eedc1a7e2761a833)
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200228004320.127142-2-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index ae532e4..46c40db 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -4974,8 +4974,21 @@ static void tgl_bw_buddy_init(struct drm_i915_private *dev_priv)
                I915_WRITE(BW_BUDDY1_CTL, BW_BUDDY_DISABLE);
                I915_WRITE(BW_BUDDY2_CTL, BW_BUDDY_DISABLE);
        } else {
+               u32 val;
+
                I915_WRITE(BW_BUDDY1_PAGE_MASK, table[i].page_mask);
                I915_WRITE(BW_BUDDY2_PAGE_MASK, table[i].page_mask);
+
+               /* Wa_22010178259:tgl */
+               val = I915_READ(BW_BUDDY1_CTL);
+               val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+               val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+               I915_WRITE(BW_BUDDY1_CTL, val);
+
+               val = I915_READ(BW_BUDDY2_CTL);
+               val &= ~BW_BUDDY_TLB_REQ_TIMER_MASK;
+               val |= REG_FIELD_PREP(BW_BUDDY_TLB_REQ_TIMER_MASK, 0x8);
+               I915_WRITE(BW_BUDDY2_CTL, val);
        }
 }
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 6cc55c1..3575fd3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7757,6 +7757,7 @@ enum {
 #define BW_BUDDY1_CTL                  _MMIO(0x45140)
 #define BW_BUDDY2_CTL                  _MMIO(0x45150)
 #define   BW_BUDDY_DISABLE             REG_BIT(31)
+#define   BW_BUDDY_TLB_REQ_TIMER_MASK  REG_GENMASK(21, 16)
 
 #define BW_BUDDY1_PAGE_MASK            _MMIO(0x45144)
 #define BW_BUDDY2_PAGE_MASK            _MMIO(0x45154)