net/mlx5: DR, Add infrastructure for supporting several steering formats

Add a struct of device specific callbacks for STE layer below dr_ste.
Each device will implement its HW-specific function, and a comon logic
from the DR code will access these functions through the new ste_ctx API.

More callbacks will follow in the subsequent patches.

Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Saeed Mahameed <saeedm@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
index d275823..171f783 100644 (file)
--- a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.c
@@ -3,7 +3,7 @@
 
 #include <linux/types.h>
 #include <linux/crc32.h>
-#include "dr_types.h"
+#include "dr_ste.h"
 
 #define DR_STE_CRC_POLY 0xEDB88320L
 #define STE_IPV4 0x1

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
new file mode 100644 (file)
index 0000000..5985092
--- /dev/null
+++ b/drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
+/* Copyright (c) 2020 NVIDIA CORPORATION. All rights reserved. */
+
+#ifndef        _DR_STE_
+#define        _DR_STE_
+
+#include "dr_types.h"
+
+#define DR_STE_CTX_BUILDER(fname) \
+       ((*build_##fname##_init)(struct mlx5dr_ste_build *sb, \
+                                struct mlx5dr_match_param *mask))
+
+struct mlx5dr_ste_ctx {
+       void DR_STE_CTX_BUILDER(eth_l2_src_dst);
+       void DR_STE_CTX_BUILDER(eth_l3_ipv6_src);
+       void DR_STE_CTX_BUILDER(eth_l3_ipv6_dst);
+       void DR_STE_CTX_BUILDER(eth_l3_ipv4_5_tuple);
+       void DR_STE_CTX_BUILDER(eth_l2_src);
+       void DR_STE_CTX_BUILDER(eth_l2_dst);
+       void DR_STE_CTX_BUILDER(eth_l2_tnl);
+       void DR_STE_CTX_BUILDER(eth_l3_ipv4_misc);
+       void DR_STE_CTX_BUILDER(eth_ipv6_l3_l4);
+       void DR_STE_CTX_BUILDER(mpls);
+       void DR_STE_CTX_BUILDER(tnl_gre);
+       void DR_STE_CTX_BUILDER(tnl_mpls);
+       int  DR_STE_CTX_BUILDER(icmp);
+       void DR_STE_CTX_BUILDER(general_purpose);
+       void DR_STE_CTX_BUILDER(eth_l4_misc);
+       void DR_STE_CTX_BUILDER(tnl_vxlan_gpe);
+       void DR_STE_CTX_BUILDER(tnl_geneve);
+       void DR_STE_CTX_BUILDER(register_0);
+       void DR_STE_CTX_BUILDER(register_1);
+       void DR_STE_CTX_BUILDER(src_gvmi_qpn);
+};
+
+#endif  /* _DR_STE_ */