drm/i915/mtl: Update CHICKEN_TRANS* register addresses

In Display version 14, Transcoder Chicken Registers have updated address.
This patch performs checks to use the right register when required.

v2: Omit display version check in i915_reg.h(Jani)
v3:
 - Remove extra whitespace introduced
 - Fix reg definitions for MTL_CHICKEN_TRANS(MattR)

Bspec: 34387, 50054
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Madhumitha Tolakanahalli Pradeep <madhumitha.tolakanahalli.pradeep@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220913183341.908028-6-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index e1eb631..de3b4fb 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -620,7 +620,10 @@ void intel_disable_transcoder(const struct intel_crtc_state *old_crtc_state)
        if (!IS_I830(dev_priv))
                val &= ~PIPECONF_ENABLE;
 
-       if (DISPLAY_VER(dev_priv) >= 12)
+       if (DISPLAY_VER(dev_priv) >= 14)
+               intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(cpu_transcoder),
+                            FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
+       else if (DISPLAY_VER(dev_priv) >= 12)
                intel_de_rmw(dev_priv, CHICKEN_TRANS(cpu_transcoder),
                             FECSTALL_DIS_DPTSTREAM_DPTTG, 0);
 
@@ -1840,7 +1843,9 @@ static void hsw_set_frame_start_delay(const struct intel_crtc_state *crtc_state)
 {
        struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
        struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
-       i915_reg_t reg = CHICKEN_TRANS(crtc_state->cpu_transcoder);
+       enum transcoder transcoder = crtc_state->cpu_transcoder;
+       i915_reg_t reg = DISPLAY_VER(dev_priv) >= 14 ? MTL_CHICKEN_TRANS(transcoder) :
+                        CHICKEN_TRANS(transcoder);
        u32 val;
 
        val = intel_de_read(dev_priv, reg);
@@ -4128,7 +4133,9 @@ static bool hsw_get_pipe_config(struct intel_crtc *crtc,
        }
 
        if (!transcoder_is_dsi(pipe_config->cpu_transcoder)) {
-               tmp = intel_de_read(dev_priv, CHICKEN_TRANS(pipe_config->cpu_transcoder));
+               tmp = intel_de_read(dev_priv, DISPLAY_VER(dev_priv) >= 14 ?
+                                   MTL_CHICKEN_TRANS(pipe_config->cpu_transcoder) :
+                                   CHICKEN_TRANS(pipe_config->cpu_transcoder));
 
                pipe_config->framestart_delay = REG_FIELD_GET(HSW_FRAME_START_DELAY_MASK, tmp) + 1;
        } else {

diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5adfd22..03604a3 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -565,7 +565,10 @@ static void intel_mst_enable_dp(struct intel_atomic_state *state,
        drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
                                 drm_atomic_get_mst_payload_state(mst_state, connector->port));
 
-       if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
+       if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable)
+               intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0,
+                            FECSTALL_DIS_DPTSTREAM_DPTTG);
+       else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable)
                intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0,
                             FECSTALL_DIS_DPTSTREAM_DPTTG);
 

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 7c46a9f..3053c17 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5728,6 +5728,13 @@
                                            [TRANSCODER_B] = _CHICKEN_TRANS_B, \
                                            [TRANSCODER_C] = _CHICKEN_TRANS_C, \
                                            [TRANSCODER_D] = _CHICKEN_TRANS_D))
+
+#define _MTL_CHICKEN_TRANS_A   0x604e0
+#define _MTL_CHICKEN_TRANS_B   0x614e0
+#define MTL_CHICKEN_TRANS(trans)       _MMIO_TRANS((trans), \
+                                                   _MTL_CHICKEN_TRANS_A, \
+                                                   _MTL_CHICKEN_TRANS_B)
+
 #define  HSW_FRAME_START_DELAY_MASK    REG_GENMASK(28, 27)
 #define  HSW_FRAME_START_DELAY(x)      REG_FIELD_PREP(HSW_FRAME_START_DELAY_MASK, x)
 #define  VSC_DATA_SEL_SOFTWARE_CONTROL REG_BIT(25) /* GLK */