drm/amd/display: add missing ABM registers

[Why]
We are currently missing some ABM registers.

[How]
Add the missing registers to dce_abm.h.

Reviewed-by: Jun Lei <jun.lei@amd.com>
Reviewed-by: Chris Park <chris.park@amd.com>
Acked-by: Hamza Mahfooz <hamza.mahfooz@amd.com>
Signed-off-by: Sridevi Arvindekar <sridevi.arvindekar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
index e6c0632..168cb70 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
+++ b/drivers/gpu/drm/amd/display/dc/dce/dce_abm.h
@@ -266,7 +266,24 @@
        type MASTER_COMM_INTERRUPT; \
        type MASTER_COMM_CMD_REG_BYTE0; \
        type MASTER_COMM_CMD_REG_BYTE1; \
-       type MASTER_COMM_CMD_REG_BYTE2
+       type MASTER_COMM_CMD_REG_BYTE2; \
+       type ABM1_HG_BIN_33_40_SHIFT_INDEX; \
+       type ABM1_HG_BIN_33_64_SHIFT_FLAG; \
+       type ABM1_HG_BIN_41_48_SHIFT_INDEX; \
+       type ABM1_HG_BIN_49_56_SHIFT_INDEX; \
+       type ABM1_HG_BIN_57_64_SHIFT_INDEX; \
+       type ABM1_HG_RESULT_DATA; \
+       type ABM1_HG_RESULT_INDEX; \
+       type ABM1_ACE_SLOPE_DATA; \
+       type ABM1_ACE_OFFSET_DATA; \
+       type ABM1_ACE_OFFSET_SLOPE_INDEX; \
+       type ABM1_ACE_THRES_INDEX; \
+       type ABM1_ACE_IGNORE_MASTER_LOCK_EN; \
+       type ABM1_ACE_READBACK_DB_REG_VALUE_EN; \
+       type ABM1_ACE_DBUF_REG_UPDATE_PENDING; \
+       type ABM1_ACE_LOCK; \
+       type ABM1_ACE_THRES_DATA_1; \
+       type ABM1_ACE_THRES_DATA_2
 
 struct dce_abm_shift {
        ABM_REG_FIELD_LIST(uint8_t);
@@ -288,6 +305,16 @@ struct dce_abm_registers {
        uint32_t DC_ABM1_LS_MIN_MAX_PIXEL_VALUE_THRES;
        uint32_t DC_ABM1_HGLS_REG_READ_PROGRESS;
        uint32_t DC_ABM1_ACE_OFFSET_SLOPE_0;
+       uint32_t DC_ABM1_ACE_OFFSET_SLOPE_DATA;
+       uint32_t DC_ABM1_ACE_PWL_CNTL;
+       uint32_t DC_ABM1_HG_BIN_33_40_SHIFT_INDEX;
+       uint32_t DC_ABM1_HG_BIN_33_64_SHIFT_FLAG;
+       uint32_t DC_ABM1_HG_BIN_41_48_SHIFT_INDEX;
+       uint32_t DC_ABM1_HG_BIN_49_56_SHIFT_INDEX;
+       uint32_t DC_ABM1_HG_BIN_57_64_SHIFT_INDEX;
+       uint32_t DC_ABM1_HG_RESULT_DATA;
+       uint32_t DC_ABM1_HG_RESULT_INDEX;
+       uint32_t DC_ABM1_ACE_THRES_DATA;
        uint32_t DC_ABM1_ACE_THRES_12;
        uint32_t MASTER_COMM_CNTL_REG;
        uint32_t MASTER_COMM_CMD_REG;